Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof

Abstract

A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

1 - 10 . (canceled) 
     
     
         11 . A nonvolatile ferroelectric memory device comprising:
 a memory cell comprising a silicon substrate including a bottom word line formed therein, a floating channel layer formed over the bottom word line and drain/source regions formed at both ends of the floating channel layer; a ferroelectric layer formed over the floating channel layer; and a word line formed over the ferroelectric layer, the memory cell being configured to induce a different channel resistance to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so as to read/write data;   a register configured to store information of the memory cell; and   a refresh control unit configured to perform a refresh operation in a given refresh cycle using the information stored in the register to improve retention characteristics of data stored in the memory cell.   
     
     
         12 . The nonvolatile ferroelectric memory device according to  claim 11 , wherein the memory cell has a double gate 1T-FET type cell structure. 
     
     
         13 . The nonvolatile ferroelectric memory device according to  claim 11 , wherein the memory cell comprises:
 an insulating layer formed in an etching region of the silicon substrate;   a bottom word line in the insulating layer enclosed by the insulating layer;   a floating channel layer formed over the bottom word line; and   an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate.   
     
     
         14 . The nonvolatile ferroelectric memory device according to  claim 13 , wherein the silicon substrate is a P-type substrate. 
     
     
         15 . The nonvolatile ferroelectric memory device according to  claim 13 , wherein the drain region is connected to a bulk connection silicon region, thereby exposing a part of the silicon substrate. 
     
     
         16 . The nonvolatile ferroelectric memory device according to  claim 15 , wherein the bulk connection silicon region is formed to have substantially the same height as that of the insulating layer. 
     
     
         17 . The nonvolatile ferroelectric memory device according to  claim 13 , further comprising a sensing line contact and a bit line contact, the sensing line contact and the bit line contact being formed over the impurity layer and arranged alternately with the word line. 
     
     
         18 . The nonvolatile ferroelectric memory device according to  claim 13 , further comprising a bit line formed over the drain region and at a top side of the silicon substrate where the insulating layer is not formed. 
     
     
         19 . The nonvolatile ferroelectric memory device according to  claim 13 , further comprising a sensing line formed over the source region and at a top side of the insulating layer where the silicon substrate is not formed. 
     
     
         20 . The nonvolatile ferroelectric memory device according to  claim 13 , wherein the impurity layer is an N+ layer. 
     
     
         21 . The nonvolatile ferroelectric memory device according to  claim 11 , further comprising a buffer insulating layer formed between the floating channel layer and the ferroelectric layer. 
     
     
         22 . The nonvolatile ferroelectric memory device according to  claim 21 , further comprising a floating conductive layer formed between the buffer insulating layer and the floating channel layer. 
     
     
         23 . A nonvolatile ferroelectric memory device comprising:
 a cell array including a plurality of nonvolatile memory cells, the nonvolatile memory cells being configured to read/write data;   a refresh control unit configured to control a refresh operation in a given cycle in response to a refresh control signal for improving retention characteristics of data stored in the memory cell to output a count address for refresh operations;   a row address control unit configured to latch and decode a row address in response to a RAS signal and an output signal from the refresh control unit and to select the count address in the refresh mode;   a column address control unit configured to latch and decode a column address in response to a CAS signal; and   an input/output logic circuit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands,   wherein the cell array further comprises:   an insulating layer formed in an etching region of a silicon substrate;   a bottom word line formed in the insulating layer and enclosed by the insulating layer;   a floating channel layer formed over the bottom word line;   an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate;   a ferroelectric layer formed over the floating channel layer; and   a word line formed over the ferroelectric layer.   
     
     
         24 . The nonvolatile ferroelectric memory device according to  claim 23 , wherein the refresh control unit comprises:
 a refresh information register configured to store various nonvolatile parameter information for controlling the refresh operation to output a refresh control signal corresponding to the parameter information;   a refresh controller configured to output a refresh signal and a refresh enable signal for performing a refresh operation in response to the refresh control signal; and   a refresh counter configured to count a refresh cycle in response to the refresh signal to output a count address.   
     
     
         25 . The nonvolatile ferroelectric memory device according to  claim 23 , further comprising a pad array unit configured to selectively output the row address and the column address with a given time difference to the row address control unit and the column address control unit. 
     
     
         26 . The nonvolatile ferroelectric memory device according to  claim 25 , wherein the row address and the column address are input through the same pad and selectively output with a given time difference. 
     
     
         27 . The nonvolatile ferroelectric memory device according to  claim 23 , wherein the row address control unit comprises:
 a row timing logic circuit configured to control a latch timing of the row address in response to the RAS signal;   a row address register configured to latch the row address depending on control of the row timing logic circuit and to selectively output one of the row address and the count address according to a refresh enable signal; and   a row decoder configured to decode an output signal from the row address register to output the signal to the cell array.   
     
     
         28 . The nonvolatile ferroelectric memory device according to  claim 23 , wherein the column address control unit comprises:
 a column timing logic circuit configured to control the latch timing of the column address in response to the CAS signal;   a column address register configured to latch the column address depending on control of the column timing logic circuit; and   a column decoder configured to decode an output signal from the column address register.   
     
     
         29 . The nonvolatile ferroelectric memory device according to  claim 23 , wherein the cell array comprises:
 a plurality of word lines arranged in a row direction;   a plurality of bottom word lines arranged in parallel with the word lines in the row direction;   a plurality of sensing lines arranged in parallel with the word lines in the row directions;   a plurality of bit lines arranged in a column direction, the bit lines being crossed with the word lines, the bottom word lines and the sensing lines; and   a plurality of unit cells arranged in a region where the word lines, the bottom word lines, the sensing lines, and the bit lines are crossed.   
     
     
         30 . The nonvolatile ferroelectric memory device according to  claim 29 , wherein the plurality of unit cells share the bit lines and the sensing lines with adjacent unit cells. 
     
     
         31 . The nonvolatile ferroelectric memory device according to  claim 29 , wherein the plurality of unit cells share one active region, and share bit line contacts and sensing line contacts with adjacent unit cells. 
     
     
         32 . The nonvolatile ferroelectric memory device according to  claim 29 , wherein the cell array further comprises:
 a sense amplifier configured to sense and amplify data of the bit line;   a write driver configured to output a driving voltage for writing the data in the unit cell to the bit line; and   a register configured to store output data of the sense amplifier temporarily.   
     
     
         33 - 55 . (canceled)