Ternary content addressable memory embedded in a central processing unit

Abstract

An arithmetic logic unit ( 140 ) improves the processing of information. The arithmetic logic unit ( 140 ) includes a register unit ( 250 ), a ternary content addressable memory ( 260 ), and an operations unit ( 270 ).

1 . In a network device, a central processing unit (CPU) comprising:
 an arithmetic logic unit; and   a ternary content addressable memory operatively coupled to the arithmetic logic unit and configured to perform one or more matching operations.   
     
     
         2 . The CPU of  claim 1  wherein the one or more matching operations includes a network packet processing operation. 
     
     
         3 . The CPU of  claim 2  wherein the packet processing operation includes an address lookup operation. 
     
     
         4 . The CPU of  claim 3  wherein the address lookup operation includes an Internet Protocol (IP) address lookup operation. 
     
     
         5 . The CPU of  claim 1  wherein the one or more matching operations includes a packet stuff/unstuff operation. 
     
     
         6 . The CPU of  claim 1  wherein the one or more matching operations includes a packet classification operation. 
     
     
         7 . The CPU of  claim 1  wherein the ternary content addressable memory is located within the arithmetic logic unit. 
     
     
         8 . The CPU of  claim 1  further comprising:
 a first register configured to store a first 32-bit operand; and 
 a second register configured to store a second 32-bit operand. 
 
     
     
         9 . The CPU of  claim 8  wherein the ternary content addressable memory performs the one or more matching operations based on at least one of the first and second 32-bit operands. 
     
     
         10 . The CPU of  claim 8  wherein the ternary content addressable memory includes a memory array including a group of 64-bit entries, and
 wherein, when performing the one or more matching operations, the ternary content addressable memory compares higher order bits of each entry of the memory array to the first 32-bit operand and compares lower order bits of each entry of the memory array to the second 32-bit operand. 
 
     
     
         11 . The CPU of  claim 1  wherein the ternary content addressable memory includes a memory array that includes a group of 64-bit entries. 
     
     
         12 . The CPU of  claim 11  wherein the memory array comprises 32 entries. 
     
     
         13 . The CPU of  claim 1  wherein, when performing the one or more matching operations, the ternary content addressable memory is configured to:
 compare an operand to a group of entries. 
 
     
     
         14 . The CPU of  claim 13  wherein the ternary content addressable memory is further configured to:
 set a first flag when the operand fails to match an entry in the group of entries, and 
 set a second flag when the operand matches multiple entries of the group of entries. 
 
     
     
         15 . The CPU of  claim 13  wherein, prior to comparing, the ternary content addressable memory is configured to:
 sequentially load the group of entries from a succession of mask/value pairs transferred to the ternary content addressable memory. 
 
     
     
         16 . A method for processing packets in a network device, comprising:
 receiving a packet; and   processing the packet using a ternary content addressable memory resident within a processing unit of the network device.   
     
     
         17 . The method of  claim 16  wherein the processing unit includes an arithmetic logic unit, and
 wherein the ternary content addressable memory is located within the arithmetic logic unit. 
 
     
     
         18 . The method of  claim 16  wherein the processing includes performing a matching operation using information in a header of the packet. 
     
     
         19 . The method of  claim 18  wherein the processing includes a packet classification operation. 
     
     
         20 . A system for forwarding packets in a network device, comprising:
 means for receiving at least one packet; and   means for processing the packet using a ternary content addressable memory resident within a central processing unit of the network device.   
     
     
         21 . An arithmetic logic unit comprising:
 a register unit;
 an operations unit; and 
   a ternary content addressable memory coupled to the register unit and operations unit.