Low power synchronous memory command address scheme

Abstract

A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver.

1 . A synchronous memory array comprising:
 a command receiver, for receiving a command signal;   an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and   a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver.   
     
     
         2 . The synchronous memory array of  claim 1 , further comprising:
 a system clock coupled to the decoder, for decoding the command signal to generate the address receiver enable signal.   
     
     
         3 . The synchronous memory array of  claim 1 , wherein if the decoded command signal indicates that the address receiver must be enabled the address receiver enable signal will be generated and if the decoded command signal indicates that the address receiver does not need to be enabled the address receiver enable signal will not be generated. 
     
     
         4 . The synchronous memory array of  claim 1 , further comprising:
 a system clock for latching the address signal for at least a clock cycle of the system clock.   
     
     
         5 . The synchronous memory array of  claim 4  wherein the address signal is latched according to a decoding time of the command signal. 
     
     
         6 . The synchronous memory array of  claim 1 , wherein the synchronous memory array complies with a Double Data Rate-4 (DDR4) specification. 
     
     
         7 . The synchronous memory array of  claim 1 , wherein when the address receiver is turned on, the address receiver is then turned off after a period of time in which no further command signal for the address receiver is received.