Linear Transformation Circuit

Abstract

A first device includes a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit as an input to receive a vector having N digital values and an output to output N first output signals. The linear transformation circuit optionally includes a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H. The linear transformation circuit includes a digital-to-analog conversion (DAC) circuit coupled to the output of the sign-adjustment circuit. Outputs from the DAC circuit are summed to produce an output.

1 . A device, comprising:
 a first output-selection circuit having an input to receive a vector having N digital values, and wherein the first output-selection circuit selects a first subset of the N digital values in accordance with a first set of coefficients H 1 ; and   a first digital-to-analog-conversion (DAC) circuit coupled to N outputs from the first output-selection circuit, the first DAC circuit including a first analog weight α 1 , wherein N outputs from the first DAC circuit are summed.   
     
     
         2 . The device of  claim 1 , wherein summation of the N outputs from the first DAC circuit occurs at a current summation node. 
     
     
         3 . The device of  claim 1 , wherein the first set of coefficients H 1  and the first analog weight α 1  correspond to a decomposition of an IDFT, and wherein the output corresponds to the IDFT of the vector. 
     
     
         4 . The device of  claim 1 , further comprising:
 a second output-selection circuit having an input to receive the vector, and wherein the second output-selection circuit selects a second subset of the N digital values in accordance with a second set of coefficients H 2 ; and   a second digital-to-analog-conversion (DAC) circuit coupled to N outputs from the second output-selection circuit, wherein the second DAC circuit includes a second analog weight α 2 ,   wherein N outputs from the second DAC circuit are summed and combined with the N outputs from the first DAC circuit to produce the output.   
     
     
         5 . The device of  claim 4 , wherein the first set of coefficients H 1  and the second set of coefficients H 2  comprise coefficients having values of 0, 1 and −1. 
     
     
         6 . The device of  claim 4 , wherein the first output-selection circuit includes N XOR gates and the second output-selection circuit includes N XOR gates. 
     
     
         7 . The device of  claim 4 , wherein the output has a radix of M. 
     
     
         8 . The device of  claim 7 , wherein M equals N. 
     
     
         9 . The device of  claim 4 , wherein the first DAC circuit and the second DAC circuit each include N DACs. 
     
     
         10 . The device of  claim 4 , wherein the first analog weight α 1  and the second analog weight α 2  are selected from the group including 1 and 0.707. 
     
     
         11 . A method, comprising:
 receiving a vector having N digital values;   selecting a first subset of the N digital values in accordance with a first set of coefficients H 1 ;   performing digital-to-analog-conversion on the first subset of the N digital values in accordance with a first analog weight α 1  to produce a first plurality of analog signals; and   summing the first plurality of analog signals to produce an output.   
     
     
         12 . The method of  claim 11 , further comprising:
 selecting a second subset of the N digital values in accordance with a second set of coefficients H 2 ;   performing digital-to-analog-conversion on the second subset of the N digital values in accordance with a second analog weight α 2  to produce a second plurality of values; and   summing the second plurality of analog values with the first plurality of analog signals to produce the output.   
     
     
         13 . The method of  claim 12 , wherein the first set of coefficients H 1  and the second set of coefficients H 2  comprise coefficients having values of 0, 1 and −1. 
     
     
         14 . The method of  claim 12 , wherein selecting the first subset is performed using a first set of N XOR gates and selecting the second subset is performed using a second set of N XOR gates. 
     
     
         15 . The method of  claim 12 , wherein the output has a radix of M. 
     
     
         16 . The method of  claim 15 , wherein M equals N. 
     
     
         17 . The method of  claim 12 , wherein the first analog weight α 1  and the second analog weight α 2  are selected from the group including 1 and 0.707. 
     
     
         18 . The method of  claim 11 , wherein summing the first plurality of analog signals comprises summing the first plurality of analog signals at a current summation node. 
     
     
         19 . The method of  claim 11 , wherein the first set of coefficients H 1  and the first analog weight α 1  correspond to a decomposition of an IDFT, and wherein the output corresponds to the IDFT of the vector.