US2011205811A1PendingUtilityA1

Semiconductor device and method of controlling the same

Assignee: HONDA YASUHIKOPriority: Jun 29, 2006Filed: May 6, 2011Published: Aug 25, 2011
Est. expiryJun 29, 2026(expired)· nominal 20-yr term from priority
Inventors:Yasuhiko Honda
G11C 29/20H10B 69/00H10B 41/35
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Claims

Abstract

A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device.

Claims

exact text as granted — not AI-modified
1 . A method of controlling a semiconductor device having first and second semiconductor storage devices comprising:
 initializing an address signal;   setting a first address of the first semiconductor storage device in the address signal to read data from the memory cell array of the first semiconductor storage device;   issuing a write command to the second semiconductor storage device;   writing the data into the second semiconductor storage device;   making a decision of whether or not the data has been written into the second semiconductor storage device;   if the result of the decision is that the data has not been written into the second semiconductor storage device, carrying out writing of data again;   if the result of the decision is that the data has been written into the second semiconductor storage device, making a decision of whether or not the first address has reached a predetermined value; and   if the first address has not reached the predetermined value, setting a second address different from the first address by the second semiconductor storage device.

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