Vertical type semiconductor device, method of manufacturing a vertical type semiconductor device and method of operating a vertical semiconductor device

Abstract

A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.

1 . A method of manufacturing a vertical pillar semiconductor device comprising:
 forming a first impurity region in a substrate;   forming a single crystalline semiconductor pattern having a pillar shape perpendicular to the substrate;   forming a second impurity region in an upper portion of the single crystalline semiconductor pattern;   forming a gate insulation layer structure including a insulation layer pattern, a charge storage pattern and dielectric layer pattern on a sidewall of the single crystalline semiconductor pattern; and   forming a gate electrode on the gate insulation layer structure, the gate electrode opposite the single crystalline semiconductor pattern and having an upper face lower than that of the single crystalline semiconductor pattern.   
     
     
         2 . The method of  claim 1 , further comprising:
 storing a charge in the charge storage pattern in order to expand a memory window.   
     
     
         3 . The method of  claim 1 , wherein the single crystalline semiconductor pattern is formed by a laser epitaxial growth (LEG) process or a selective epitaxial growth (SEG) process. 
     
     
         4 . The method of  claim 1 , wherein the charge storage layer pattern is formed using a material having charge trap sites. 
     
     
         5 . The method of  claim 4 , wherein the charge storage layer pattern includes at least one of silicon nitride and metal oxide. 
     
     
         6 . The method of  claim 1 , further comprising:
 forming a first hard mask pattern enclosing an upper sidewall of the single crystalline semiconductor pattern,   wherein the gate insulation layer structure has a linear shape and is on a bottom surface of the first hard mask pattern, a sidewall of the single crystalline semiconductor pattern and the substrate.   
     
     
         7 . The method of  claim 1 , further comprising:
 forming a channel doping region below a portion of the single crystalline semiconductor pattern configured to contact the gate insulation layer structure, the channel doping region changing a threshold voltage using a pair of electrons and holes generated according to electric conditions applied to the gate electrode, the first impurity region and the second impurity region.   
     
     
         8 . The method of  claim 6 , wherein forming the first hard mask pattern includes forming the first hard mask pattern to have an upper face even with a surface of the single crystalline semiconductor pattern. 
     
     
         9 . The method of  claim 1 , further comprising:
 forming a pad insulation layer pattern between the substrate and a lower surface of the gate electrode,   wherein the pad insulation layer pattern includes silicon nitride.   
     
     
         10 . The method of  claim 6 , further comprising:
 forming first and second insulating interlayers on the first hard mask pattern;   forming at least one bit line on the second insulating interlayer;   forming a second hard mask pattern on the at least one bit line; and   forming at least one spacer on a sidewall of the at least one bit line.   
     
     
         11 . The method of  claim 10 , further comprising:
 a third insulating interlayer covering the at least one bit line;   a contact plug formed through the second and third insulating interlayers to contact an upper face of the single crystalline semiconductor pattern; and   a wiring on the contact plug.   
     
     
         12 . A method of operating a DRAM device comprising:
 providing one transistor per cell of the DRAM device, the transistor having a gate insulation layer structure including a charge storage pattern;   storing charge in the charge storage pattern for obtaining a memory window;   recording data in a channel doping region of the transistor; and   reading the recorded data.   
     
     
         13 . The method of  claim 12 , further comprising:
 adjusting the memory window by changing a programming voltage for storing the charge in the charge storage pattern.