Electronic devices

Abstract

A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.

1 . A method for forming a transistor comprising:
 depositing an electrically conductive layer onto a substrate;   embossing the substrate and the conductive layer such that a portion of the conductive layer is pushed into the substrate thereby forming a depressed region and electrically insulating the portion of the conducting layer in the depressed region from the remaining at least one region of the electrically conductive layer;   at least one portion of the conductive layer forming an electrode of the transistor.   
     
     
         2 . A method as claimed in  claim 1 , wherein the portion of the electrically conductive layer in the depressed region and a portion of the conductive layer in the remaining region form source and drain electrodes of the transistor. 
     
     
         3 . A method as claimed in  claim 1 , wherein the depressed region separates and electrically insulates at least two remaining regions of the conductive layer, wherein at least two regions form source and drain electrodes of the transistor. 
     
     
         4 . A method as claimed in  claim 1 , wherein the electrically conductive layer in the depressed region forms a floating conducting bridge in a channel of the transistor. 
     
     
         5 . A method as claimed in any of  claims 1 , wherein the method further comprises the step of depositing at least one additional non-planarizing layer on top of the embossed substrate, such that the topographic profile of each non-planarizing layer conforms to that of the substrate. 
     
     
         6 . A method as claimed in  claim 5 , wherein the method further comprises the step of depositing at least one pattern of a material onto one of the non-planarizing layers. 
     
     
         7 . A method as claimed in  claim 6 , wherein at least one pattern of a material is deposited onto a depressed region of the non-planarizing layer, the material deposited such that the lateral location of the material is defined by the shape of the non-planarizing layer. 
     
     
         8 . A method as claimed in  claim 7 , wherein the material deposited into the depressed region of the non-planarizing layer defines an active region of the transistor whereby the active region is laterally aligned with the topographic profile of the non-planarizing layer. 
     
     
         9 . A method as claimed in  claim 6 , wherein the material is a conductive or semiconductive material. 
     
     
         10 . A method as claimed in  claim 9 , wherein the pattern of a material comprises a gate electrode. 
     
     
         11 . A method as claimed in  claim 5 , wherein the at least one additional non-planarizing layer comprises depositing a first non-planarizing layer and a second non-planarizing layer. 
     
     
         12 . A method as claimed in  claim 11 , wherein said first non-planarizing layer is a semiconductor layer. 
     
     
         13 . A method as claimed in  claim 11 , wherein said second non-planarizing layer is a dielectric layer. 
     
     
         14 . A method as claimed in  claim 1 , wherein the substrate is a flexible electrically insulating substrate. 
     
     
         15 . A method as claimed in  claim 14 , wherein the flexible electrically insulating substrate is one of poly(ethleneterephtalate) (PET), polyethersulphone (PES) or polyethemaphtalene (PEN). 
     
     
         16 . A method as claimed in  claim 1 , wherein the substrate is a rigid substrate containing at least one flexible polymer layer that is electrically insulating. 
     
     
         17 . A method as claimed in  claim 6 , further comprising the step of, prior to the deposition of at least one pattern of a material, performing a surface modification process on the non-planarizing layer that has a different effect on relatively raised regions of the non-planarizing layer in comparison to relatively depressed regions of the non-planarizing layer, so as to generate a surface energy contrast between the relatively raised and relatively depressed regions of the non-planarizing layer in order to confine the deposition of the at least one pattern of a material to the depressed region. 
     
     
         18 . A method as claimed in  claim 17 , wherein the surface modification process comprises using a flat stamp to deposit a surface energy barrier in the raised regions of the non-planarizing layer. 
     
     
         19 . A method as claimed in  claim 1 , wherein one or both of the sides along the length of the boundary between the depressed region and the raised region is non linear in the plane of the substrate. 
     
     
         20 . A method as claimed in  claim 1 , wherein a layer of semiconducting material is deposited onto the substrate prior to the step of depositing the layer of conductive material onto the substrate. 
     
     
         21 . A method as claimed in  claim 1 , wherein the substrate comprises a layer of semiconducting material that forms part of the active layer of the transistor. 
     
     
         22 . A method as claimed in  claim 21 , further comprising the steps of:
 coating the embossed structure with a non-planarizing layer of gate dielectric; and   depositing a gate electrode onto the layer of gate dielectric layer, such that the gate electrode is aligned with the embossed region of the substrate.   
     
     
         23 . A method as claimed in  claim 22 , wherein the gate electrode is confined by a surface energy barrier to a depressed region of the gate dielectric conformal to the depressed region of the substrate.