Digital radiographic flat-panel imaging array with dual height semiconductor and method of making same

Abstract

Method of manufacturing imaging arrays can include providing a silicon tile having a first surface and a second, opposite surface. A buried dielectric layer is formed in the silicon tile between the first and second surfaces to define a bottom silicon layer between the first surface and the dielectric layer. A separation boundary is formed in the silicon tile between the second surface and the dielectric layer to define a top silicon layer between the dielectric layer and the separation boundary and a removable silicon layer between the separation boundary and the second surface. An oxide layer formed on the first surface of the silicon tile and the silicon tile is bonded to a glass substrate at the oxide layer. The silicon tile is separated at the separation boundary to remove the removable silicon layer, exposing the top silicon layer. Semiconductive elements are formed using the exposed top silicon layer.

1 . An imaging array comprising:
 an insulating substrate;   a single crystal silicon tile having a buried dielectric layer, the dielectric layer separating a bottom silicon portion proximate a first surface of the silicon tile from a top silicon layer proximate a second surface of the silicon tile, the first surface of the silicon tile being secured to the glass substrate;   a plurality of photosensitive elements formed from the silicon tile and having a first thickness; and   a plurality of readout elements formed from the silicon tile and having a second thickness, less than the first thickness.   
     
     
         2 . The imaging array of  claim 1 , wherein the plurality of readout elements comprise at least one of a transistor, a diode switch, a CCD, a bi-polar transistor, and a field effect transistor. 
     
     
         3 . The imaging array of  claim 2 , wherein the plurality of readout elements comprise MOS transistors formed in the bottom silicon portion of the silicon layer. 
     
     
         4 . The imaging array of  claim 3 , further comprising a dielectric formed on the bottom silicon layer, and a gate electrode formed on the dielectric. 
     
     
         5 . The imaging array of  claim 4 , further comprising a gate electrode formed on the buried dielectric layer of the silicon layer. 
     
     
         6 . The imaging array of  claim 1 , further comprising trenches separating the plurality of photosensitive elements from the plurality of readout elements. 
     
     
         7 . The imaging array of  claim 1 , wherein the plurality of readout elements have the top silicon layer removed to provide the second thickness. 
     
     
         8 . The imaging array of  claim 7 , wherein the plurality of readout elements comprise transistors formed in the bottom silicon portion of the silicon layer. 
     
     
         9 . The imaging array of  claim 8 , wherein the transistors comprise a gate electrode formed over the bottom silicon portion of the silicon layer, wherein the gate electrode is on a gate insulating layer. 
     
     
         10 . The imaging array of  claim 9 , wherein the gate insulating layer is the buried dielectric layer or an additional dielectric layer. 
     
     
         11 . The imaging array of  claim 10 , wherein the plurality of photosensitive elements are separated from the plurality of readout elements by removing portions of the top silicon layer, the dielectric layer and the bottom silicon layer between the photosensitive elements and the readout elements. 
     
     
         12 . The imaging array of  claim 1 , wherein one or more of the readout elements and the photosensitive elements comprise doped regions, wherein the doped regions are formed on one or both of the top silicon layer and the bottom silicon layer, and wherein a portion of the bottom silicon layer in a photosensitive element area is doped. 
     
     
         13 . The imaging array of  claim 1 , wherein the plurality of photosensitive elements and the plurality of readout elements are formed in the top silicon layer. 
     
     
         14 . The imaging array of  claim 1 , wherein portions of the top silicon layer are thinned. 
     
     
         15 . The imaging array of  claim 14 , wherein the plurality of readout elements are formed at the thinned portions of the top silicon layer. 
     
     
         16 . The imaging array of  claim 1 , wherein the silicon tile is bonded by anodic bonding to the insulating substrate, wherein the insulating substrate is a glass substrate. 
     
     
         17 . The imaging array of  claim 1 , wherein the plurality of photosensitive element comprise at least one of a p-n junction photodiode, a p-i-n junction photodiode, an MIS photosensor, a phototransistor, a charge coupled device, a charge injection device, a photoconductor, a pinned photodiode, or an avalanche photodiode. 
     
     
         18 . The imaging array of  claim 1 , wherein the top silicon layer is between about 500 nm and about 4000 nm thick, wherein the bottom silicon layer is between about 10 nm and about 200 nm thick.