Ferroelectric passive memory cell, device and method of manufacture thereof

Abstract

A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.

1 . A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another. 
     
     
         2 . Memory element according to  claim 1 , wherein said second electrode system comprises a plurality of conducting pins, which are part of a read-out and/or data-input device. 
     
     
         3 . Memory element according to  claim 1 , wherein said passive memory element only comprises organic materials. 
     
     
         4 . A first passive memory device comprising at least one passive ferroelectric memory element and at least one substrate at least one of said substrates having at least one conductive surface or surface layer on the at least one side provided with said passive ferroelectric memory element, said passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out and/or data-input purposes only, a plurality of conducting pins isolated from one another; and wherein, with the exception of said first electrode system being the conductive surface of a metallic substrate, said systems are printable using conventional printing processes. 
     
     
         5 . First passive memory device according to  claim 4 , wherein said element system further comprises voids resulting in contact between said first and said second electrode systems. 
     
     
         6 . First passive memory device according to  claim 4 , wherein said element system further comprises insulating elements not having ferroelectric properties under read-out or data-input conditions. 
     
     
         7 . First passive memory device according to  claim 4 , wherein said first passive memory device is exclusive of metallic silicon. 
     
     
         8 . First passive memory device according to  claim 4 , wherein said second electrode system is an electrode pattern on a second substrate. 
     
     
         9 . First passive memory device according to  claim 8 , wherein said electrode pattern on said second substrate is laminated to said element system comprising at least one ferroelectric element thereby forming a device sandwiched between two substrates. 
     
     
         10 . First passive memory device according to  claim 8 , wherein said electrode pattern on said second substrate is brought into contact with said element system for read-out and/or data-input purposes only. 
     
     
         11 . First passive memory device according to  claim 4 , wherein said first passive memory device is transparent. 
     
     
         12 . First passive memory device according to  claim 4 , wherein said passive ferroelectric memory device is overprinted with an image or a homogeneously coloured or opaque layer to visually hide said electrode systems. 
     
     
         13 . First passive memory device according to  claim 4 , wherein a coloured or opaque foil is laminated over said passive ferroelectric memory device to visually hide the location of said electrode systems. 
     
     
         14 . First passive memory device according to  claim 4 , wherein at least one of said first and second patterned electrode systems comprises an inorganic conducting medium or an organic conducting medium. 
     
     
         15 . First passive memory device according to  claim 14 , wherein said organic conducting medium is an intrinsically conductive organic polymer. 
     
     
         16 . First passive memory device according to  claim 15 , wherein said intrinsically conductive organic polymer is a polythiophene, a polyaniline or a polypyrrole. 
     
     
         17 . First passive memory device according to  claim 15 , wherein said polythiophene is a poly(3,4-dioxyalkylenethiophene). 
     
     
         18 . First passive memory device according to  claim 15 , wherein said polythiophene is poly(3,4-dioxyethylenethiophene). 
     
     
         19 . A first precursor for said first passive memory device comprising a substrate and on at least one side of said substrate: a conductive surface of said substrate or a conductive layer on said substrate, an element system comprising an organic ferroelectric element on said conductive surface or said conductive layer. 
     
     
         20 . A second precursor for said first passive memory device comprising a substrate and on at least one side of said substrate: a conductive surface of said substrate or a conductive layer on said substrate, an element system comprising an organic ferroelectric element on said conductive surface or said conductive layer and a plurality of isolated conductive areas provided for contact, for read-out and/or data-input purposes only, with a plurality of conducting pins isolated from one another. 
     
     
         21 . A process for providing a first passive memory device comprising at least one passive ferroelectric memory element and at least one substrate at least one of said substrates having at least one conductive surface or surface layer on the at least one side provided with said passive ferroelectric memory element, said passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer;
 wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out and/or data-input purposes only, a plurality of conducting pins isolated from one another; and wherein, with the exception of said first electrode system being the conductive surface of a metallic substrate, said systems are printable using conventional printing processes, comprising the steps of: providing said at least one substrate, realizing said conductive layer on said substrate if the substrate is non-metallic; realizing an element system comprising at least one ferroelectric element on said conductive surface or conductive layer, providing aa electrode pattern or a plurality of isolated conducting areas on said element system, wherein at least one of the steps of optionally providing a conductive layer, providing an element system and providing a plurality of isolated conducting areas is realized with a conventional printing process.   
     
     
         22 . Process for providing a first passive memory device according to  claim 21 , wherein all of the steps of optionally providing a conductive layer, providing an element system and providing a plurality of isolated conducting areas are realized with conventional printing processes. 
     
     
         23 . Process for providing a first passive memory device according to  claim 21 , wherein said at least one conventional printing process is a non-impact printing process. 
     
     
         24 . Process for providing a first passive memory device according to  claim 21  or  22 , wherein said at least one conventional printing process is an impact printing process. 
     
     
         25 . Process for providing a first passive memory device according to  claim 21 , wherein said conventional printing process is selected from the group consisting of ink-jet printing, intaglio printing, screen printing, flexographic printing, offset printing, stamp printing, gravure printing, electrophotographic printing, electrographic printing and thermal and laser-induced processes. 
     
     
         26 . Process for providing a first passive memory device according to anyone of  claims 21  to  25 , wherein said element system further comprises voids resulting in contact between said first and said second electrode systems. 
     
     
         27 . Process for providing a first passive memory device according to  claim 21 , wherein said element system further comprises insulating elements not having ferroelectric properties under read-out or data-input conditions. 
     
     
         28 . A second passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is an electrode pattern; and wherein said second electrode system is an electrode pattern and wherein said first electrode system, said second electrode system and said element system are all printable with conventional printing techniques. 
     
     
         29 . A second passive memory device, said passive memory device comprising at least one substrate and a passive memory element on at least one side of said at least one substrate, said passive memory element comprising a first patterned electrode system, a second patterned electrode system, an element system comprising at least one ferroelectric element between said first patterned electrode system and said second patterned electrode system; and wherein said second electrode system is an electrode pattern and wherein said first electrode system, said second electrode system and said element system are all printable with conventional printing techniques. 
     
     
         30 . A process for providing a second passive memory device, said passive memory device comprising a substrate and a passive memory element on at least one side of said at least one substrate, said passive memory element comprising a first patterned electrode system, a second patterned electrode system, an element system comprising at least one ferroelectric element between said first patterned electrode system and said second patterned electrode system, comprising the steps of: realizing a first electrode pattern on a non-conductive surface of a substrate, providing said element system on said first electrode pattern and providing a second electrode pattern on said element system, wherein the steps of providing a first patterned electrode system, providing an organic ferroelectric layer and providing a second electrode system are all realized with a conventional printing process. 
     
     
         31 . Process for providing a second passive memory device according to  claim 3 D, wherein said provision of said first patterned electrode system includes patterning a pre-coated conductive layer in a one pass printing step. 
     
     
         32 . Process for providing a second passive memory device according to  claim 31 , wherein said pre-coated conductive layer comprises an intrinsically conductive polymer. 
     
     
         33 . Process for providing a second passive memory device according to  claim 32 , wherein said intrincially conductive polymer is a substituted or unsubstituted polythiophene, a substituted or unsubstituted polyaniline or a substituted or unsubstituted polypyrrole. 
     
     
         34 . Process for providing a second passive memory element according to  claim 33 , wherein said substituted or unsubstituted polythiophene is represented by formula (I): 
       
         
           
           
               
               
           
         
       
       wherein n is larger than 1 and each of R 1  and R 2  independently represents hydrogen or an optionally substituted C 1-4  alkyl group or together represent an optionally substituted C 1-4  alkylene group or an optionally substituted cycloalkylene group, preferably an ethylene group, an optionally alkyl-substituted methylene group, an optionally C 1-12  alkyl- or phenyl-substituted ethylene group, a 1,3-propylene group or a 1,2-cyclohexylene group. 
     
     
         35 . Process for providing a second passive memory element according to  claim 3 D, wherein said passive memory element only comprises organic materials. 
     
     
         36 . Process for providing a second passive memory element according to  claim 3 D, wherein said conventional printing process is a non-impact printing process. 
     
     
         37 . Process for providing a second passive memory element according to  claim 30 , wherein said conventional printing process is an impact printing process. 
     
     
         38 . Process for providing a second passive memory element according to  claim 30 , wherein said conventional printing process is selected from the group consisting of ink-jet printing, intaglio printing, screen printing, flexographic printing, offset printing, stamp printing, gravure printing, electrophotographic printing, electrographic printing and thermal and laser-induced processes. 
     
     
         40 . Process for providing a second passive memory element according to  claim 30 , wherein said element system further comprises voids resulting in contact between said first and said second electrode systems. 
     
     
         41 . Process for providing a second passive memory element according to  claim 30 , wherein said element system further comprises insulating elements not having ferroelectric properties under read-out or data-input conditions.