US2011212547A1PendingUtilityA1

Methods for monitoring the amount of metal contamination imparted into wafers during a semiconductor process

Assignee: MEMC ELECTRONIC MATERIALSPriority: Dec 23, 2009Filed: May 11, 2011Published: Sep 1, 2011
Est. expiryDec 23, 2029(~3.4 yrs left)· nominal 20-yr term from priority
H10P 74/235H10P 74/203H10D 86/00H10P 74/00H10P 72/0604
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Claims

Abstract

Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Claims

exact text as granted — not AI-modified
1 . A method for monitoring the amount of metal contamination imparted into wafers during a semiconductor process, the method comprising:
 exposing at least one silicon-on-insulator structure to the semiconductor process, the silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer;   evaluating metal contamination indicators of the silicon-on-insulator structures; and   verifying whether the amount of metal contamination imparted into semiconductor wafers is acceptable.   
     
     
         2 . The method as set forth in  claim 1  comprising adjusting the semiconductor process to reduce that amount of metal contamination induced into wafers during the semiconductor process when the amount of metal contamination is determined to be unacceptable. 
     
     
         3 . The method as set forth in  claim 1  wherein the metal contamination indicators are selected from metal precipitates; pits, cavities and/or holes; and scattered light reflected from the surface of the silicon-on-insulator structure. 
     
     
         4 . The method as set forth in  claim 1  wherein metal contamination is verified by comparing the metal contamination indicators to metal contamination indicators gathered when the level of contamination was determined to be acceptable. 
     
     
         5 . The method as set forth in  claim 1  wherein the semiconductor process is selected from a group consisting of polishing, cleaning, bond strength enhancing thermal treatment, epitaxy, oxide stripping, plasma activation, wet chemical etching, gas phase chemical etching, high temperature annealing, ion implantation and oxidation.

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