Device manufacturing method

Abstract

There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.

1 . A device manufacturing method, comprising:
 forming the plurality of electronic devices on a wafer;   forming a plurality of circuits under test on the wafer;   measuring electric characteristics of the plurality of circuits under test; and   judging whether the respective electronic devices are good or defective, based on positions at which the plurality of circuits under test are provided and the electric characteristics of the respective circuits under test.   
     
     
         2 . The device manufacturing method according to  claim 1 ,
 wherein forming the circuits under test includes:   forming, in each of the circuits under test, a plurality of transistors under measurement provided in electrically parallel;   forming, in each of the circuits under test, a selecting section which sequentially selects the respective transistors under measurement; and   forming, in each of the circuits under test, an output section which sequentially outputs source voltages of the transistors under measurement sequentially selected by the selecting section.   
     
     
         3 . The device manufacturing method according to  claim 2 ,
 forming the circuits under test further includes:   forming, in each of the circuits under test, a plurality of current sources which are provided correspondingly to the plurality of transistors under measurement for defining source-drain currents of the corresponding transistors under measurement; and   forming, in each of the circuits under test, a plurality of gate voltage control sections which are provided correspondingly to the plurality of transistors under measurement for applying a predetermined gate voltage to gate terminals of the corresponding transistors under measurement.   
     
     
         4 . The device manufacturing method according to  claim 3 ,
 wherein measuring electric characteristics includes:   controlling the output section in each of the circuits under test to sequentially output the source voltages of the transistors under measurement sequentially selected by the selecting section;   controlling the respective gate voltage control sections in each of the circuits under test to apply the gate voltage for controlling the corresponding transistors under measurement to be ON to the gate terminals of the corresponding transistors under measurement; and   calculating, in each of the circuits under test, a threshold voltage of each of the transistors under measurement, based on the gate voltage of the transistor under measurement and the source voltage of the transistor under measurement output from the output section.   
     
     
         5 . The device manufacturing method according to  claim 1 ,
 wherein forming the circuits under test includes:   forming, in each of the circuits under test, a plurality of transistors under measurement which are provided in electrically parallel;   forming, in each of the circuits under test, a plurality of gate voltage control sections which are provided correspondingly to the plurality of transistors under measurement for applying a predetermined gate voltage to gate terminals of the corresponding transistors under measurement;   forming, in each of the circuits under test, a plurality of voltage applying sections which are provided correspondingly to the plurality of transistors under measurement for applying voltages to source terminals and drain terminals of the corresponding transistors under measurement to control a voltage applied to gate insulating films of the transistors under measurement to be generally constant;   forming, in each of the circuits under test, a plurality of integral capacitors which are provided correspondingly to the plurality of transistors under measurement for integrating gate leak currents output from the source terminals and the drain terminals of the corresponding transistors under measurement;   forming, in each of the circuits under test, a selecting section which sequentially selects the respective transistors under measurement; and   forming, in each of the circuits under test, an output section which sequentially outputs voltages of the integral capacitors corresponding to the transistors under measurement sequentially selected by the selecting section.   
     
     
         6 . The device manufacturing method according to  claim 5 ,
 wherein measuring electric characteristics includes:   controlling, in each of the circuits under test, the gate voltage control sections to apply a predetermined gate voltage to the gate terminals of the transistors under measurement, and controlling the voltage applying sections to control the voltage applied to the gate insulating films of the transistors under measurement to be generally constant; and   calculating, in each of the circuits under test, the gate leak current of each of the transistors under measurement, based on an amount of change in the voltage output from the output section during a predetermined period.