System and method for manufacturing double epi n-type lateral diffusion metal oxide semiconductor transistors

Abstract

A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current.

1 . A method for manufacturing an N-type lateral diffusion metal oxide semiconductor transistor, wherein the method comprises the steps of:
 forming a P-type substrate;   forming a first N-type buried layer on the P-type substrate;   forming a first epitaxial layer on the first N-type buried layer;   forming a second N-type buried layer on the first N-type buried layer;   forming a second epitaxial layer on the second N-type buried layer.   
     
     
         2 . The method as set forth in  claim 1  further comprising the steps of
 forming an N-type sinker through the second epitaxial layer down to the second N-type buried layer; 
 forming an Ndrift region in the second epitaxial layer down to the second N-type buried layer; and 
 forming shallow trench isolation regions over the N-type sinker and over the Ndrift region. 
 
     
     
         3 . The method as set forth in  claim 2  further comprising the steps of
 forming a gate structure over the Ndrift region; and 
 forming a P-type body in the Ndrift region; and 
 forming a source region in the P-type body; and 
 forming a drain region in the Ndrift region. 
 
     
     
         4 . The method as set forth in  claim 3  wherein a combined width of the first N-type buried layer and of the second N-type buried layer minimizes an operation of a parasitic NPN bipolar transistor in the N-type lateral diffusion metal oxide semiconductor transistor. 
     
     
         5 . The method as set forth in  claim 3  wherein a peak doping profile of the first N-type buried layer and a peak doping profile of the second N-type buried layer minimize an operation of a parasitic NPN bipolar transistor in the N-type lateral diffusion metal oxide semiconductor transistor. 
     
     
         6 . An N-type lateral diffusion metal oxide semiconductor transistor comprising:
 a P-type substrate;   a first N-type buried layer on the P-type substrate;   a first epitaxial layer on the first N-type buried layer;   a second N-type buried layer on the first N-type buried layer; and   a second epitaxial layer on the second N-type buried layer.   
     
     
         7 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 6  further comprising:
 an N-type sinker through the second epitaxial layer down to the second N-type buried layer; 
 an Ndrift region in the second epitaxial layer down to the second N-type buried layer; and 
 shallow trench isolation regions over the N-type sinker and over the Ndrift region. 
 
     
     
         8 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 7  further comprising:
 a gate structure over the Ndrift region; and 
 a P-type body in the Ndrift region; and 
 a source region in the P-type body; and 
 a drain region in the Ndrift region. 
 
     
     
         9 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 8  wherein a combined width of the first N-type buried layer and of the second N-type buried layer minimizes an operation of a parasitic NPN bipolar transistor in the N-type lateral diffusion metal oxide semiconductor transistor. 
     
     
         10 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 8  wherein a peak doping profile of the first N-type buried layer and a peak doping profile of the second N-type buried layer minimize an operation of a parasitic NPN bipolar transistor in the N-type lateral diffusion metal oxide semiconductor transistor. 
     
     
         11 .- 15 . (canceled) 
     
     
         16 . An N-type lateral diffusion metal oxide semiconductor transistor comprising:
 a P-type substrate;   a first N-type buried layer on the P-type substrate;   a first epitaxial layer on the first N-type buried layer;   a second N-type buried layer on a first portion of the first N-type buried layer;   a P-type buried layer on a second portion of the first N-type buried layer; and   a second epitaxial layer on the second N-type buried layer and on the P-type buried layer.   
     
     
         17 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 16  further comprising:
 an N-type sinker through the second epitaxial layer down to the second N-type buried layer; 
 an Ndrift region in the second epitaxial layer that extends down to the P-type buried layer; 
 a P well region in the second epitaxial layer that extends down to the P-type buried layer; and 
 shallow trench isolation regions over the N-type sinker and over the Ndrift region and over the P well region. 
 
     
     
         18 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 17  further comprising:
 a gate structure over the Ndrift region; and 
 a P-type body in the Ndrift region; and 
 a source region in the P-type body; and 
 a drain region in the Ndrift region. 
 
     
     
         19 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 18  wherein a protection NPN bipolar transistor is formed within the N-type lateral diffusion metal oxide semiconductor transistor that minimizes an operation of a parasitic NPN bipolar transistor within the N-type lateral diffusion metal oxide semiconductor transistor. 
     
     
         20 . The N-type lateral diffusion metal oxide semiconductor transistor as set forth in  claim 19  wherein
 a collector of the protection NPN bipolar transistor is connected to the first N-type buried layer; 
 a base of the protection NPN bipolar transistor is connected to the P well region; and 
 an emitter of the protection NPN bipolar transistor is connected to the Ndrift region through the first N-type buried layer and through the P-type buried layer.