Memory power management systems and methods

Abstract

Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

1 - 11 . (canceled) 
     
     
         12 . A method for managing power of a memory array, the method comprising:
 providing an active operating voltage to provide power to the memory array;   selectably coupling a respective selectably coupleable diode to each of a plurality of memory blocks of the memory array to provide a minimum memory retention voltage to power each of the plurality of memory blocks;   selectably decoupling a respective selectably coupleable diode from a selected memory block of the memory array to provide an active operating voltage to power the selected memory block; and reading from or writing to the selected memory.   
     
     
         13 . The method of  claim 12 , further comprising decoupling each selectably coupleable diode from each respective memory block of the memory array and providing a minimum memory retention voltage to power the memory array. 
     
     
         14 . The method of  claim 13 , wherein providing an active operating voltage to provide power to the memory array comprises providing an active operating voltage from a first low dropout (LDO) regulator and providing a minimum memory retention voltage to power the memory array comprises providing a minimum memory retention voltage from a second LDO regulator. 
     
     
         15 . The method of  claim 12 , further comprising reading the minimum memory retention voltage from a storage device and setting the minimum memory retention voltage based on the reading. 
     
     
         16 . The method of  claim 12 , wherein the minimum memory retention is derived from a minimum peripheral voltage, which is the minimum voltage that one or more peripheral circuits need to reliably read and/or write from the memory array. 
     
     
         17 - 20 . (canceled) 
     
     
         21 . An apparatus, comprising:
 circuitry for providing an active operating voltage to provide power to the memory array;   circuitry for selectably coupling a respective selectably coupleable diode to each of a plurality of memory blocks of the memory array to provide a minimum memory retention voltage to power each of the plurality of memory blocks;   circuitry for selectably decoupling a respective selectably coupleable diode from a selected memory block of the memory array to provide an active operating voltage to power the selected memory block; and   reading from or writing to the selected memory.   
     
     
         22 . The apparatus of  claim 21 , further comprising circuitry for decoupling each selectably coupleable diode from each respective memory block of the memory array and providing a minimum memory retention voltage to power the memory array. 
     
     
         23 . The apparatus of  claim 22 , wherein providing an active operating voltage to provide power to the memory array comprises providing an active operating voltage from a first low dropout (LDO) regulator and providing a minimum memory retention voltage to power the memory array comprises providing a minimum memory retention voltage from a second LDO regulator. 
     
     
         24 . The apparatus of  claim 21 , further comprising circuitry for reading the minimum memory retention voltage from a storage device and setting the minimum memory retention voltage based on the reading. 
     
     
         25 . The method of  claim 21 , wherein the minimum memory retention is derived from a minimum peripheral voltage, which is the minimum voltage that one or more peripheral circuits need to reliably read and/or write from the memory array.