Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same

Abstract

Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

1 . A memory cell structure, comprising:
 a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes doped with impurities, a floating body region, and a buffer region between one of the first and second nodes and the floating body, wherein the buffer region has a lower impurity concentration that the adjacent node or the floating body and wherein the buffer region covers the entire boundary of the one of the first and second nodes; and   a gate structure on the silicon layer.   
     
     
         2 . The memory cell structure of  claim 1 , wherein the buffer region has a height the same as the one of the first and second nodes. 
     
     
         3 . The memory cell structure of  claim 1 , wherein the buffer region contacts the insulator. 
     
     
         4 . A memory cell structure, comprising:
 a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes doped with impurities, a floating body region having a floating body length therebetween, and a buffer region between one of the first and second nodes and the floating body, wherein the buffer region has a lower impurity concentration that the adjacent node or the floating body; and   a gate structure having a gate length on the silicon layer, wherein the floating body length is greater than the gate length.   
     
     
         5 . A memory cell structure, comprising:
 a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including an emitter/source and a collector/drain doped with impurities, a floating body region, and an auxiliary body region between the emitter/source and the floating body, wherein the auxiliary body region has a lower impurity concentration than that of the floating body; and   a gate structure on the silicon layer.   
     
     
         6 . The memory cell structure of  claim 5 , wherein the auxiliary body region covers the entire of the emitter/source. 
     
     
         7 . The memory cell structure of  claim 5 , wherein the floating body region is longer than the auxiliary body region. 
     
     
         8 . A memory cell structure, comprising:
 a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes doped with impurities, a floating body region, and an extended body region adjacent to the floating body region; and   a gate structure on the silicon layer.   
     
     
         9 . The memory cell structure of  claim 8 , wherein the extended body region extends in a direction orthogonal to a direction of the first and second nodes and the floating body. 
     
     
         10 . The memory cell structure of  claim 8 , wherein the extended body region extends in a direction under the gate structure. 
     
     
         11 . A memory cell structure, comprising:
 an insulating layer on a substrate;   a silicon pattern on the insulating layer and including a first node, second node and a floating body region; and   a gate surrounding the floating body region,   wherein the length of the gate is less than the floating body region and wherein a voltage difference between voltages applied to the first and second nodes for a given voltage applied to the gate induces a bipolar junction operation.   
     
     
         12 . The memory cell of  claim 11 , further comprising:
 a buffer region between the floating body region and one of the first node and the second node, wherein the buffer region has a lower impurity concentration than that of the one of the first node and the second node.   
     
     
         13 . A memory cell structure, comprising:
 an insulating layer on a substrate;   a silicon pattern on the insulating layer, which including a first node, second node and a floating body region;   an extended body region on the floating body region; and   a gate structure surrounding the floating body region and the extended body region.   
     
     
         14 . The memory cell of  claim 13 , wherein the gate length is less than the length of the floating body region. 
     
     
         15 . The memory cell of  claim 13 , further comprising:
 a buffer region between the floating body region and one of the first node and the second node, wherein the buffer region has a lower impurity concentration than that of the one of the first node and the second node.   
     
     
         16 . A memory cell structure, comprising:
 a silicon-on-insulator structure including a substrate, an insulator, and a silicon layer, the silicon layer including first and second nodes, a floating body region; and   a gate on the floating body region,   wherein the length of gate is less than the length of the floating body, and wherein a difference between voltages applied to the first and second nodes for a given voltage applied to the gate induces a bipolar junction operation.   
     
     
         17 . The memory cell structure of  claim 16 , wherein the gate does not overlap the first and second nodes. 
     
     
         18 . The memory cell structure of  claim 16 , wherein the gate does not overlap at least one of the first and second nodes. 
     
     
         19 . The memory cell structure of  claim 18 , wherein the one the first and second nodes receives a higher applied voltage for the bipolar junction operation.