Btsc encoder

Abstract

The disclosed BTSC encoder includes a left high pass filter means for receiving a digital left channel audio signal and for digitally high pass filtering the digital left channel audio signal and thereby generating a digital left filtered signal; a right high pass filter means for receiving a digital right channel audio signal and for digitally high pass filtering the digital right channel audio signal and thereby generating a digital right filtered signal; a matrix means for receiving the digital left and digital right filtered signals, and including means for summing the digital left and digital right filtered signals and thereby generating a digital sum signal, and including means for subtracting one of the digital left and digital right filtered signals from the other of the digital left and digital right filtered signals and thereby generating a digital difference signal; a difference channel processing means for digitally processing the digital difference signal; and a sum channel processing means for digitally processing the digital sum signal.

1 . A digital signal processor comprising:
 (a) an input section configured to receive one or more digital signals and generate therefrom a digital sum signal and a digital difference signal;   (b) a digital difference channel section comprising (i) an adaptive signal weighting system configured to dynamically vary the amplitude and phase of the digital difference signal, and (ii) a frequency shifting system configured to alter the frequency of the digital difference signal according to the BTSC standard to produce a modified digital difference signal;   (c) a digital sum channel section comprising one or more digital filters configured to alter the amplitude and phase of the digital sum signal according to the BTSC standard so as to produce a modified digital sum signal; and   (d) an output section configured to combine the modified digital difference signal and modified digital sum signal and subsequently form one or more digital output signals;   wherein the digital signal processor is configured to provide a frequency response in the digital domain that is substantially equal to the corresponding analog frequency response specified by the BTSC standard.   
     
     
         2 . A digital signal processor according to  claim 1 , wherein the frequency shifting system is configured to alter the frequency of the digital difference signal by substantially 31.468 kHz. 
     
     
         3 . A digital signal processor comprising:
 (a) an input section configured to receive one or more digital signals and generate therefrom a digital sum signal and digital difference signal;   (b) a digital difference channel section comprising (i) an adaptive signal weighting system configured to dynamically vary the amplitude and phase of the digital difference signal, and (ii) a multiplier system configured to alter the frequency of the digital difference signal according to the BTSC standard to produce a modified digital difference signal;   (c) a digital sum channel section comprising one or more digital filters configured to alter the frequency and phase of the digital sum signal according to the BTSC standard to produce a modified digital sum signal; and   (d) an output section configured to combine the modified digital difference signal and modified digital sum signal and form one or more digital output signals;   wherein the digital signal processor is configured to provide a frequency response in the digital domain that is substantially equal to the corresponding analog frequency response specified by the BTSC standard.   
     
     
         4 . A digital signal processor comprising:
 (a) an input section configured to receive one or more digital input signals;   (b) a sum-channel processing section configured to generate a sum-channel signal according to the BTSC standard from the digital input signals;   (c) a difference-channel processing section configured to generate and filter a difference-channel signal according to the BTSC standard from the digital input signals; and   (d) a combining section for transforming the sum-channel signal and the difference-channel signal into one or more output signals according to the BTSC standard;   wherein the digital signal processor is configured to provide a frequency response in the digital domain that is substantially equal to the corresponding analog frequency response specified by the BTSC standard.