US2011243333A1PendingUtilityA1

Btsc encoder

53
Assignee: THAT CORPPriority: Jun 7, 1996Filed: Jun 29, 2011Published: Oct 6, 2011
Est. expiryJun 7, 2016(expired)· nominal 20-yr term from priority
H04R 5/04H04H 20/88H04S 5/02H04N 5/602G10L 19/008H04N 7/06
53
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Claims

Abstract

The disclosed BTSC encoder includes a left high pass filter means for receiving a digital left channel audio signal and for digitally high pass filtering the digital left channel audio signal and thereby generating a digital left filtered signal; a right high pass filter means for receiving a digital right channel audio signal and for digitally high pass filtering the digital right channel audio signal and thereby generating a digital right filtered signal; a matrix means for receiving the digital left and digital right filtered signals, and including means for summing the digital left and digital right filtered signals and thereby generating a digital sum signal, and including means for subtracting one of the digital left and digital right filtered signals from the other of the digital left and digital right filtered signals and thereby generating a digital difference signal; a difference channel processing means for digitally processing the digital difference signal; and a sum channel processing means for digitally processing the digital sum signal.

Claims

exact text as granted — not AI-modified
1 . A digital signal processor comprising:
 (a) an input section configured to receive one or more digital signals and derive therefrom a digital sum signal and a digital difference signal;   (b) a digital difference channel section comprising (i) an adaptive signal weighting system configured to dynamically vary the amplitude and phase of the digital difference signal, and (ii) a frequency shifting system configured to alter the frequency of the digital difference signal according to the BTSC standard to produce a modified digital difference signal;   (c) a digital sum channel section comprising one or more digital filters for altering the amplitude and phase of the digital sum signal according to the BTSC standard so as to produce a modified digital sum signal; and   (d) an output section configured to combine the modified digital difference signal and modified digital sum signal and subsequently form one or more digital output signals;   wherein the difference between the modified digital difference channel signal and the modified digital sum channel signal, for a given frequency and level, conforms substantially with the difference specified by the BTSC standard.   
     
     
         2 . A digital signal processor according to  claim 1 , wherein the frequency shifting system is configured to alter the frequency of the digital difference signal by substantially 31.468 kHz. 
     
     
         3 . A digital signal processor comprising:
 (a) an input section configured to receive one or more digital signals and derive therefrom a digital sum signal and digital difference signal;   (b) a digital difference channel section comprising (i) an adaptive signal weighting system configured to dynamically vary the amplitude and phase of the digital difference signal, and (ii) a multiplier system configured to alter the frequency of the digital difference signal according to the BTSC standard to produce a modified digital difference signal;   (c) a digital sum channel section comprising one or more digital filters for altering the frequency and phase of the digital sum signal according to the BTSC standard to produce a modified digital sum signal; and   (d) an output section for combining the modified digital difference signal and modified digital sum signal to form two digital output signals;   wherein the difference between the two digital output signals, for a given frequency and level, conforms substantially with the difference specified by the BTSC standard.   
     
     
         4 . A digital signal processor comprising:
 (a) an input section configured to receive one or more digital input signals;   (b) a sum-channel processing section for creating and conditioning a sum-channel signal according to the BTSC standard from the digital input signals;   (c) a difference-channel processing section for creating and filtering a difference-channel signal according to the BTSC standard from the digital input signals; and   (d) a combining section for transforming the sum-channel signal and the difference-channel signal into two digital output signals;   wherein the difference between the two digital output signals, for a given frequency and level, conforms substantially with the difference specified by the BTSC standard.

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