Method of Manufacturing Nonvolatile Memory Device

Abstract

In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions are etched to form trenches for isolation in the respective isolation regions. The trenches for isolation are filled with an insulating layer to form isolation layers in the respective trenches. A lower passivation layer is formed over an entire surface including top surfaces of the isolation layers. A first oxide layer is formed over an entire surface including the lower passivation layer. Meta-stable bond structures within the lower passivation layer are changed to stable bonds. A nitride layer, a second oxide layer, and an upper passivation layer are sequentially formed over an entire surface including the first oxide layer.

1 . A method of manufacturing a nonvolatile memory device, comprising:
 forming a tunnel insulating layer and a charge trap layer over a semiconductor substrate that defines active regions and isolation regions;   forming trenches for isolation in the respective isolation regions by etching the tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions;   filling the trenches for isolation with an insulating layer to form isolation layers in the respective trenches;   forming a lower passivation layer over an entire surface including top surfaces of the isolation layers;   forming a first oxide layer over an entire surface including the lower passivation layer;   changing meta-stable bonds within the lower passivation layer to stable bonds; and   forming a nitride layer, a second oxide layer and an upper passivation layer over an entire surface including the first oxide layer.   
     
     
         2 . The method of  claim 1 , comprising changing the meta-stable bonds with the lower passivation layer to stable bonds using a radical plasma process 
     
     
         3 . The method of  claim 2 , comprising performing the radical plasma process to increase a density of the first oxide layer, to improve a film quality of the first oxide layer, and to change Si x N y -based materials within the lower passivation layer to SiON-based materials having a higher bond energy than the Si x N y -based materials. 
     
     
         4 . The method of  claim 2 , comprising performing the radical plasma process by flowing O 2  gas at a flow rate of 100 sccm to 500 sccm and Ar gas at a flow rate of 500 sccm to 5000 sccm at a temperature in the range of 400° C. to 600° C. at a pressure in the range of 0.01 Torr to 100 Torr in an atmosphere in which oxygen can be radicalized. 
     
     
         5 . The method of  claim 1 , comprising forming the lower passivation layer using a plasma nitrification treatment process. 
     
     
         6 . The method of  claim 5 , comprising performing the plasma nitrification treatment process by flowing N 2  gas at a flow rate of 100 sccm to 500 sccm and Ar gas at a flow rate of 500 sccm to 5000 sccm at a temperature in the range of 400° C. to 600° C. at a pressure in the range of 0.01 Torr to 100 Torr. 
     
     
         7 . The method of  claim 1 , further comprising performing an ion implantation process after forming the lower passivation layer. 
     
     
         8 . The method of  claim 1 , further comprising performing a nitrification treatment process using N 2  gas after forming the lower passivation layer. 
     
     
         9 . The method of  claim 1 , further comprising performing a radical plasma process after forming the upper passivation layer. 
     
     
         10 . The method of  claim 1 , comprising forming the upper passivation layer using a plasma nitrification treatment process. 
     
     
         11 . A method of manufacturing a nonvolatile memory device, comprising:
 forming a tunnel insulating layer and a charge trap layer over a semiconductor substrate that defines active regions and isolation regions;   forming trenches for isolation in the respective isolation regions by etching the charge trap layer, the tunnel insulating layer, and the semiconductor substrate formed in the isolation regions, wherein the etched charge trap layer has sidewalls and a top surface;   filling trenches with an insulating layer to form isolation layers in the respective trenches;   forming a lower passivation layer on the sidewalls and the top surface of the charge trap layer;   forming a dielectric layer over an entire surface including the lower passivation layer; and   forming an upper passivation layer over an entire surface including the dielectric layer after forming the dielectric layer.   
     
     
         12 . The method of  claim 11 , comprising forming the lower passivation layer using a plasma nitrification treatment process. 
     
     
         13 . The method of  claim 11 , comprising forming the lower passivation layer by:
 performing a plasma nitrification treatment process to form a nitride layer over an entire surface including the charge trap layer and the isolation layers; and   selectively etching the nitride layer formed over the isolation layers.   
     
     
         14 . The method of  claim 13 , comprising selectively etching the nitride layer using a combination of an etch process using diluted HF (DHF) having a concentration in the range of 1:1 to 1:500, an O 3  cleaning process, a dry cleaning process, and a cleaning process using SC-1 solution. 
     
     
         15 . The method of  claim 13 , wherein a bond energy of the nitride layer formed over the sidewalls and the top surface of the charge trap layer is higher than a bond energy of the nitride layer formed over the isolation layers. 
     
     
         16 . The method of  claim 13 , wherein the nitride layer formed over the charge trap layer is Si 3 N 4 , and the nitride layer over the insulating layer for isolation is SiON. 
     
     
         17 . The method of  claim 11 , comprising forming the upper passivation layer using a plasma nitrification treatment process. 
     
     
         18 . A method of manufacturing a nonvolatile memory device, comprising:
 forming a tunnel insulating layer and a charge trap layer over a semiconductor substrate that defines active regions and isolation regions;   forming trenches for isolation in the respective isolation regions by etching the tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions;   filling the trenches for isolation with an insulating layer to form isolation layers in the respective trenches;   forming a dielectric layer over an entire surface including the isolation layers; and,   performing a radical plasma process after forming the dielectric layer.   
     
     
         19 . The method of  claim 18 , further comprising forming a passivation layer over an entire surface including the dielectric layer before performing the radical plasma process. 
     
     
         20 . The method of  claim 19 , comprising forming the passivation layer using a plasma nitrification treatment process.