Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same

Abstract

Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

1 . A nonvolatile memory device, comprising:
 a string of nonvolatile memory cells on a substrate, said string of nonvolatile memory cells comprising:
 a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells; 
 a second vertical stack of nonvolatile memory cells on the substrate and a ground selection transistor on the second vertical stack of nonvolatile memory cells; and 
 a conjunction doped semiconductor region within the substrate, electrically connecting the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells. 
   
     
     
         2 . The device of  claim 1 , wherein the first vertical stack of nonvolatile memory cells comprises a first vertical stack of gate electrodes and a first vertical-type semiconductor active region on the first vertical stack of gate electrodes; wherein the second vertical stack of nonvolatile memory cells comprises a second vertical stack of gate electrodes and a second vertical-type semiconductor active region on the second vertical stack of gate electrodes; and wherein the first and second vertical-type semiconductor active regions contact the conjunction doped semiconductor region. 
     
     
         3 . The device of  claim 2 , wherein the first and second vertical-type semiconductor active regions are of first conductivity type and the conjunction doped semiconductor region is of second conductivity type opposite the first conductivity type. 
     
     
         4 . The device of  claim 1 , further comprising a bit line electrically connected to a terminal of the string selection transistor and a source line electrically connected to a terminal of the ground selection transistor. 
     
     
         5 . The device of  claim 1 , wherein the first and second vertical stacks of nonvolatile memory cells and the conjunction doped semiconductor region collectively form a single NAND-type string of nonvolatile memory cells. 
     
     
         6 . A nonvolatile memory device, comprising:
 a string of nonvolatile memory cells on a substrate, said string of nonvolatile memory cells comprising:
 a first plurality of nonvolatile memory cells comprising a first vertical stack of gate electrodes and a first vertical active region on the first vertical stack of gate electrodes, on the substrate; 
 a second plurality of nonvolatile memory cells comprising a second vertical stack of gate electrodes and a second vertical active region on the second vertical stack of gate electrodes, on the substrate; 
 a string selection transistor having a gate electrode on the first vertical stack of gate electrodes; 
 a ground selection transistor having a gate electrode on the second vertical stack of gate electrodes; and 
 a semiconductor region of first conductivity type in the substrate, said semiconductor region forming at least one of a P-N rectifying junction and doped/undoped semiconductor junction with the first and second vertical active regions. 
   
     
     
         7 . The device of  claim 6 , further comprising a bit line electrically connected to a terminal of the string selection transistor and a source line electrically connected to a terminal of the ground selection transistor. 
     
     
         8 . A three-dimensional semiconductor memory device comprising:
 a first gate stack comprising first dielectric patterns and first gates that are alternately and repeatedly stacked over a substrate, the first gates comprising a plurality of first cell gates being stacked and a string selection gate over an uppermost first cell gate;   a second gate stack comprising second dielectric patterns and second gates that are alternately and repeatedly stacked over the substrate at one side of the first gate stack, the second gates comprising a plurality of second cell gates being stacked and a ground selection gate over an uppermost second cell gate;   an active structure comprising a first vertical-type active portion overlapping sidewalls of the first gates and a second vertical-type active portion overlapping sidewalls of the second gates;   a gate dielectric layer between the first gates and the first vertical-type active portion, and between the second gates and the second vertical-type active portion; and   a conjunction doped region in the substrate, the conjunction doped region being connected to lower ends of the first and second vertical-type active portions.   
     
     
         9 . The three-dimensional semiconductor memory device of  claim 8 , wherein:
 a lowermost first gate is a lowermost first cell gate;   a lowermost second gate is a lowermost second cell gate; and   a first cell transistor comprising the lowermost first cell gate is connected in series to a second cell transistor comprising the lowermost second cell gate through the conjunction doped region.   
     
     
         10 . The three-dimensional semiconductor memory device of  claim 8 , wherein major carriers in the conjunction doped region are identical to carriers in channels generated in the first and second vertical-type active portions. 
     
     
         11 . The three-dimensional semiconductor memory device of  claim 10 , wherein:
 the substrate is doped with a first-type dopant;   the conjunction doped region is doped with a second-type dopant; and   the active structure is doped with the first-type dopant or undoped.   
     
     
         12 . The three-dimensional semiconductor memory device of  claim 8 , further comprising:
 a bit line electrically connected to an upper end of the first vertical-type active portion; and   a source line electrically connected to an upper end of the second vertical-type active portion.   
     
     
         13 . The three-dimensional semiconductor memory device of  claim 12 , wherein the bit line and the source line are located at different levels with respect to a top surface of the substrate. 
     
     
         14 . The three-dimensional semiconductor memory device of  claim 8 , wherein the gate dielectric layer between the first cell gate and the first vertical-type active portion, and between the second cell gate and the second vertical-type active portion comprises an information storage element. 
     
     
         15 . The three-dimensional semiconductor memory device of  claim 8 , wherein:
 the first and second gate stacks extend side by side in one direction parallel to a top surface of the substrate;   the first and second vertical-type active portions are disposed over the substrate between the first and second gate stacks;   the first vertical-type active portion overlaps portions of one sidewalls of the first gates extending in the one direction; and   the second vertical-type active portion overlaps portions of one sidewalls of the second gates extending in the one direction.   
     
     
         16 . The three-dimensional semiconductor memory device of  claim 15 , wherein:
 the active structure is provided in plurality over the substrate;   the plurality of the active structures are disposed between the first and second gate stacks and spaced from each other in the one direction;   the conjunction doped region is provided in plurality in the substrate between the first and second gate stacks;   the plurality of the conjunction doped regions are spaced from each other in the one direction; and   each of the conjunction doped regions is connected to lower ends of the first and second vertical-type active portions of each of the active structures.   
     
     
         17 . The three-dimensional semiconductor memory device of  claim 16 , wherein a top surface of the substrate between the conjunction doped regions is lower than a top surface of the conjunction doped region to define a recess region,
 the three-dimensional semiconductor memory device further comprising:   a filling-dielectric pattern filling a space between the first and second gate stacks and between the active structures adjacent to each other,   wherein the filling-dielectric pattern extends downward to fill the recess region.   
     
     
         18 . The three-dimensional semiconductor memory device of  claim 16 , further comprising:
 a field dielectric pattern formed in the substrate and defining a plurality of base active portions that are spaced from each other,   wherein the conjunction doped regions are formed in the base active portions, respectively.   
     
     
         19 . The three-dimensional semiconductor memory device of  claim 15 , further comprising:
 a filling-dielectric pattern between the first and second vertical-type active portions.   
     
     
         20 . The three-dimensional semiconductor memory device of  claim 19 , wherein the active structure further comprises a planar portion between the filling-dielectric pattern and the substrate, and the planar portion is connected to the first and second vertical-type active portions. 
     
     
         21 . The three-dimensional semiconductor memory device of  claim 8 , wherein the first vertical-type active portion penetrates the first dielectric patterns and the first gates continuously, and overlaps sidewalls of the first gates, which are surrounding the first vertical-type active portion, and
 the second vertical-type active portion penetrates the second dielectric patterns and the second gates continuously, and overlaps sidewalls of the second gates, which are surrounding the second vertical-type active portion.   
     
     
         22 . The three-dimensional semiconductor memory device of  claim 21 , wherein:
 the first and second gate stacks extend side by side in one direction parallel to a top surface of the substrate;   the active structure is provided in plurality;   the first vertical-type active portions respectively comprised in the plurality of the active structures are spaced from each other in the one direction, and penetrate the first gate stack;   the second vertical-type active portion respectively comprised in the plurality of the active structures are spaced from each other in the one direction, and penetrate the second gate stack;   the conjunction doped region is provided in plurality in the substrate;   the plurality of the conjunction doped regions are spaced from each other in the one direction; and   each of the conjunction doped regions is connected to lower ends of the first and second vertical-type active portions in each of the active structures.   
     
     
         23 . The three-dimensional semiconductor memory device of  claim 22 , further comprising a field dielectric pattern formed in the substrate and defining base active portions spaced from each other, wherein the conjunction doped regions are formed in the base active portions, respectively.