Continuous asymmetrically sloped shallow trench isolation region

Abstract

This document discusses, among other things, a semiconductor device, and a method of forming a semiconductor device, having a shallow trench isolation (STI) region including a continuous, asymmetrically sloped sidewall.

1 . A semiconductor device, comprising:
 a substrate including a semiconductor region defining a working top surface in which the semiconductor device is formed;   a drain region;   a source region; and   a shallow trench isolation (STI) region in the substrate between the drain region and the source region, the STI region including a continuous, asymmetrically sloped sidewall.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the continuous, asymmetrically sloped sidewall includes a first region proximate the base of the STI region having a first slope and a second region proximate the top surface of the substrate having a second slope, the second slope different than the first slope. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the first slope is substantially constant along the first region, and wherein the second slope is substantially constant along the second region. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the STI region includes a depth from the top surface of the substrate to the base of the STI region, and wherein each of the first and second regions of the continuous, asymmetrically sloped sidewall are greater than one-tenth of the depth of the STI region. 
     
     
         5 . The semiconductor device of  claim 4 , wherein each of the first and second regions of the continuous, asymmetrically sloped sidewall are greater than one-fifth of the depth of the STI region. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the depth of the STI region substantially corresponds to the sum of the lengths of the first and second regions of the continuous, asymmetrically sloped sidewall. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the STI region includes a first non-asymmetrically sloped sidewall having a substantially linear slope and a second asymmetrically sloped sidewall. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the first asymmetrically sloped sidewall is proximate the source region and the second non-asymmetrically sloped sidewall is proximate the drain region. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the semiconductor device includes a metal oxide semiconductor field effect transistor (MOSFET). 
     
     
         10 . The semiconductor device of  claim 1 , wherein the semiconductor device includes a lateral double-diffused field metal oxide semiconductor (LDMOS) device. 
     
     
         11 . A semiconductor device, comprising:
 a shallow trench isolation (STI) region in a substrate between a drain region and a source region of the semiconductor device, the STI region including first and second sidewall, the first sidewall proximate the drain region and the second sidewall proximate the source region, wherein the second sidewall includes a continuous, asymmetrically sloped sidewall having at least two regions with different slopes with respect to a top surface of the substrate.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the continuous, asymmetrically sloped sidewall includes a first region proximate the base of the STI region having a first slope, and a second region proximate the top surface of the substrate having a second slope, the second slope different than the first slope. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the first slope is substantially constant along the first region, and wherein the second slope is substantially constant along the second region. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the STI region includes a depth from the top surface of the substrate to the base of the STI region, and wherein each of the first and second regions of the continuous, asymmetrically sloped sidewall are greater than one-tenth of the depth of the STI region. 
     
     
         15 . The semiconductor device of  claim 14 , wherein each of the first and second regions of the continuous, asymmetrically sloped sidewall are greater than one-fifth of the depth of the STI region. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the depth of the STI region substantially corresponds to the sum of the lengths of the first and second regions of the continuous, asymmetrically sloped sidewall. 
     
     
         17 . The semiconductor device of  claim 11 , wherein the first sidewall includes a non-asymmetrically sloped sidewall having a substantially linear slope. 
     
     
         18 . The semiconductor device of  claim 11 , wherein the semiconductor device includes a metal oxide semiconductor field effect transistor (MOSFET). 
     
     
         19 . The semiconductor device of  claim 11 , wherein the semiconductor device includes a lateral double-diffused field metal oxide semiconductor (LDMOS) device. 
     
     
         20 . A semiconductor device, comprising:
 a substrate including a semiconductor region defining a working top surface in which the semiconductor device is formed;   a drain region;   a source region; and   a shallow trench isolation (STI) region in a substrate between the drain region and the source region, the STI region including first and second sidewall, the first sidewall proximate the drain region and the second sidewall proximate the source region, wherein the second sidewall includes a continuous, asymmetrically sloped sidewall including a first region having a first slope substantially constant along the first region and a second region having a second slope substantially constant along the second region, wherein the first slope is different than the second slope, and wherein the STI region includes a depth from the working top surface of the substrate to the base of the STI region, and wherein each of the first and second regions have a depth greater than one-fifth of the depth of the STI region.