US2011254054A1PendingUtilityA1

Semiconductor device

Assignee: PANASONIC CORPPriority: Jan 8, 2009Filed: Jun 29, 2011Published: Oct 20, 2011
Est. expiryJan 8, 2029(~2.4 yrs left)· nominal 20-yr term from priority
Inventors:Satoru Itou
H10P 30/225H10D 64/01318H10P 30/208H10D 30/608H10D 64/667H10P 30/204H10D 64/691H10D 64/685H10D 30/0213H10D 84/0174H10D 84/0167H10D 84/038H10D 84/017H10D 64/015H10D 62/021H10D 30/797H10D 30/792H10D 30/0275H10D 30/0227
31
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A semiconductor device has at least an n-type MIS transistor, which includes a first gate insulating film formed on a first semiconductor region in a semiconductor substrate, a first gate electrode formed on the first gate insulating film, first sidewalls formed on the side surfaces of the first gate electrode, and carbon-containing silicon regions formed laterally outside the first sidewalls. The top surfaces of the carbon-containing silicon regions are at a level higher than the top surface of a region in the first semiconductor region lying under the first gate insulating film.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 at least an n-type MIS transistor,   
       wherein
 the n-type MIS transistor includes
 a first gate insulating film formed on a first semiconductor region in a semiconductor substrate, 
 a first gate electrode formed on the first gate insulating film, 
 first sidewalls formed on side surfaces of the first gate electrode, 
 first silicon layers made of a first epitaxial layer found on regions in the first semiconductor region lying laterally outside the first sidewalls, and 
 carbon-containing silicon regions formed in the first silicon layers and in regions in an upper portion of the first semiconductor region lying immediately under the first silicon layers. 
 
 
     
     
         2 . The semiconductor device of  claim 1 , wherein
 the highest top surfaces of the carbon-containing silicon regions are at a level higher than the highest top surface of a region in the first semiconductor region lying immediately under the first gate insulating film.   
     
     
         3 . The semiconductor device of  claim 1 , wherein
 the maximum depth of portions of the carbon-containing silicon regions formed in the first semiconductor region is larger than the maximum thickness of the first silicon layers.   
     
     
         4 . The semiconductor device of  claim 1 , wherein
 the carbon-containing silicon regions include carbon implanted in the first silicon layers and in the regions in an upper portion of the first semiconductor region lying immediately under the first silicon layers.   
     
     
         5 . The semiconductor device of  claim 1 , wherein
 n-type impurity-diffused regions are formed in the carbon-containing silicon regions.   
     
     
         6 . The semiconductor device of  claim 1 , wherein
 each of the first sidewalls includes a first inner sidewall having an L-shaped cross-section formed on a side surface of the first gate electrode and a first outer sidewall formed on the first inner sidewall.   
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a stress insulating film formed above the first semiconductor region, configured to cause a tensile stress in a channel region in the first semiconductor region in a gate length direction.   
     
     
         8 . The semiconductor device of  claim 7 , wherein
 each of the first sidewalls includes a first inner sidewall having an L-shaped cross-section formed on a side surface of the first gate electrode, and   the stress insulating film is formed in contact with an L-shaped surface of the first inner sidewall.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 first silicide layers formed on the carbon-containing silicon regions.   
     
     
         10 . The semiconductor device of  claim 9 , wherein
 the first gate electrode includes a first polysilicon film formed on the first gate insulating film, and   the semiconductor device further comprises a second silicide layer formed on the first polysilicon film.   
     
     
         11 . The semiconductor device of  claim 10 , wherein
 the first gate insulating film includes a first high-k insulating film, and   the first gate electrode includes a first metal film formed between the first gate insulating film and the first polysilicon film.   
     
     
         12 . The semiconductor device of  claim 2 , wherein
 the first gate electrode includes a first polysilicon film formed on the first gate insulating film,   the semiconductor device further comprises
 first silicide layers formed on the carbon-containing silicon regions, and 
 a second silicide layer formed on the first polysilicon film, and 
   the maximum depth of portions of the carbon-containing silicon regions formed in the first semiconductor region is larger than the maximum thickness of the first silicon layers.   
     
     
         13 . The semiconductor device of  claim 1 , wherein
 the carbon concentration of the carbon-containing silicon regions is 0.5% or more.   
     
     
         14 . The semiconductor device of  claim 1 , further comprising:
 a p-type MIS transistor,   
       wherein
 the p-type MIS transistor includes
 a second gate insulating film formed on a second semiconductor region in the semiconductor substrate, 
 a second gate electrode formed on the second gate insulating film, 
 second sidewalls formed on side surfaces of the second gate electrode, and 
 germanium-containing silicon regions formed laterally outside the second sidewalls. 
 
 
     
     
         15 . The semiconductor device of  claim 14 , wherein
 the germanium-containing silicon regions are made of a second epitaxial layer formed in recesses formed by etching regions in the second semiconductor region located laterally outside the second sidewalls.   
     
     
         16 . The semiconductor device of  claim 14 , further comprising:
 second silicon layers made of the first epitaxial layer formed on the germanium-containing silicon regions.   
     
     
         17 . The semiconductor device of  claim 16 , further comprising:
 second silicide layers formed on the second silicon layers.   
     
     
         18 . The semiconductor device of  claim 16 , wherein
 the highest top surfaces of the second silicon layers are at a level higher than the highest top surfaces of the first silicon layers.   
     
     
         19 . The semiconductor device of  claim 14 , wherein
 the second gate insulating film includes a second high-k insulating film, and   the second gate electrode includes a second metal film formed in contact with the second gate insulating film.   
     
     
         20 . The semiconductor device of  claim 14 , wherein
 the germanium concentration of the germanium-containing silicon regions is 15% or more.

Join the waitlist — get patent alerts

Track US2011254054A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.