Semiconductor integrated circuit device having reduced unit cell area and method for manufacturing the same

Abstract

A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions.

1 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate;   a plurality of word lines extending parallel to one another on the semiconductor substrate;   a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions where the word lines intersect the bit lines and a plurality of unit memory cells;   a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions;   is storage node contacts respectively formed in spaces of the unit memory cells; and   a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions,   wherein the gate electrodes of the unit memory cells adjacent to each other with the word lines interposed therebetween, are structured in such a way as to share the corresponding word lines, and the bit line contacts of the unit memory cells adjacent to each other with the bit lines interposed therebetween, contact one another in such a way as to share corresponding bit lines,   wherein any one gate electrode positioned on an even word line among the word lines is arranged between a pair of gate electrodes positioned on adjoining odd word lines, and   wherein any one bit line contact positioned on an even bit line among the bit lines is arranged between a pair of bit line contacts positioned on adjoining odd bit lines.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the gate electrodes are formed in the semiconductor substrate in a buried type. 
     
     
         3 . The semiconductor integrated circuit device according to  claim 2 , wherein an isolation layer is additionally formed in portions of the semiconductor substrate which correspond to word line regions. 
     
     
         4 . The semiconductor integrated circuit device according to  claim 3 , wherein the gate electrodes are formed in the isolation layer to have a trench structure. 
     
     
         5 . The semiconductor integrated circuit device according to  claim 4 , wherein the gate electrodes include a gate dielectric layer formed on sidewalls thereof. 
     
     
         6 . The semiconductor integrated circuit device according to  claim 2 , wherein the word lines and the gate electrodes are buried in the isolation layer. 
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , wherein the gate electrodes are arranged in a diagonal direction of the plurality of word lines and the plurality of bit lines. 
     
     
         8 . The semiconductor integrated circuit device according to  claim 7 , wherein each of the bit line contacts is positioned between a pair of adjoining gate electrodes which are arranged in the diagonal direction. 
     
     
         9 . The semiconductor integrated circuit device according to  claim 1 , wherein a length of one side of each of the word lines, the bit lines and the unit memory cells corresponds to a minimum feature is size. 
     
     
         10 . The semiconductor integrated circuit device according to  claim 1 , wherein the bit line contacts extend from the bit lines into the semiconductor substrate. 
     
     
         11 . The semiconductor integrated circuit device according to  claim 10 , wherein impurity regions are formed in portions of the semiconductor substrate which correspond to bottoms of the bit line contacts. 
     
     
         12 . The semiconductor integrated circuit device according to  claim 11 , wherein impurity regions are formed in portions of the semiconductor substrate which correspond to matrix spaces in which the storage node contacts are formed, wherein the matrix spaces are surrounded by the plurality of word lines and the plurality of bit lines. 
     
     
         13 . A semiconductor integrated circuit device comprising:
 a plurality of word lines and a plurality of bit lines which intersect each other; and   a plurality of memory cells connected with the word lines and the bit lines,   the memory cells comprising   gate electrodes positioned on the word lines on one sides of crossing regions where the word lines intersect the bit lines;   bit line contacts positioned on the bit lines on one sides of the crossing regions; and   storage node contacts formed in spaces which are surrounded by the word lines and the bit lines.   
     
     
         14 . The semiconductor integrated circuit device according to  claim 13 , wherein the gate electrodes are configured to commonly control corresponding memory cells and other memory cells which adjoin the corresponding memory cells with the word lines interposed therebetween. 
     
     
         15 . The semiconductor integrated circuit device according to  claim 14 ,
 wherein the word lines and the bit lines are formed in plural numbers, and   wherein the gate electrodes are positioned on the one sides of the crossing regions of the word lines and the bit lines, and are arranged in a diagonal direction of the word lines and the bit lines.   
     
     
         16 . The semiconductor integrated circuit device according to  claim 15 , wherein the gate electrodes are arranged such that any one gate electrode positioned on an even word line is formed between a pair of gate electrodes positioned on adjoining odd word lines. 
     
     
         17 . The semiconductor integrated circuit device according to is  claim 15 , wherein each of the bit line contacts is positioned between a pair of adjoining gate electrodes which are arranged in the diagonal direction. 
     
     
         18 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate;   an isolation layer formed in the semiconductor substrate to delimit active regions;   a plurality of word lines buried in the semiconductor substrate and extending parallel to one another with a predetermined spacing;   a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells;   a plurality of storage node contacts respectively formed in the active regions of spaces of the unit memory cells; and   a plurality of bit line contacts formed at bit line forming positions which correspond to one sides of the crossing regions,   wherein the unit memory cells adjacent to each other with the word lines interposed therebetween, are structured in such a way as to share the corresponding word lines, and bit line contacts of the unit memory cells adjacent to each other with the bit lines interposed therebetween, contact one another in such a way as to share corresponding bit lines,   wherein any one gate electrode positioned on an even word line is among the word lines is arranged between a pair of gate electrodes positioned on adjoining odd word lines, and   wherein any one bit line contact positioned on an even bit line among the bit lines is arranged between a pair of bit line contacts positioned on adjoining odd bit lines.   
     
     
         19 . The semiconductor integrated circuit device according to  claim 18 , wherein the word lines are formed in the isolation layer to have a trench structure. 
     
     
         20 . The semiconductor integrated circuit device according to  claim 19 , wherein the word lines include a gate dielectric layer formed on sidewalls thereof. 
     
     
         21 . The semiconductor integrated circuit device according to  claim 18 ,
 wherein each of the bit line contacts is positioned between a pair of storage nodes, and   wherein each of the active regions is delimited by the pair of storage nodes and the bit line contact positioned therebetween.   
     
     
         22 . The semiconductor integrated circuit device according to  claim 18 , wherein a length of one side of each of the word lines, the bit lines and matrix spaces, surrounded by the plurality of word lines and the plurality of bit lines, corresponds to a minimum feature size. 
     
     
         23 . The semiconductor integrated circuit device according to  claim 18 , wherein the bit line contacts extend from the bit lines into the semiconductor substrate. 
     
     
         24 . The semiconductor integrated circuit device according to  claim 23 , wherein impurity regions are formed in portions of the semiconductor substrate which correspond to bottoms of the bit line contacts. 
     
     
         25 . The semiconductor integrated circuit device according to  claim 23 , wherein impurity regions are formed in portions of the semiconductor substrate which correspond to matrix spaces in which the storage node contacts are formed, wherein the matrix spaces are surrounded by the plurality of word lines and the plurality of bit lines. 
     
     
         26 . The semiconductor integrated circuit device according to  claim 18 , wherein the gate electrodes are arranged in a diagonal direction of the plurality of word lines and the plurality of bit lines. 
     
     
         27 . The semiconductor integrated circuit device according to  claim 26 , wherein each of the bit line contacts is positioned between a pair of adjoining gate electrodes which are arranged in the diagonal direction. 
     
     
         28 . A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
 forming drain regions in predetermined portions of a semiconductor substrate;   forming first bit line contacts in the semiconductor substrate in such a way as to contact the drain regions;   forming word lines in preselected portions of the semiconductor substrate;   forming source regions by implanting impurities into portions of the semiconductor substrate which correspond to both sides of the word lines and both sides of the first bit line contacts;   forming selectively second bit line contacts on the first bit line contacts;   forming bit lines over the second bit line contacts in a direction crossing with the word lines; and   forming storage node contacts over the source regions.   
     
     
         29 . The method according to  claim 28 , wherein the step of forming the word lines comprises the steps of:
 forming trenches in the preselected portions of the semiconductor substrate;   forming a gate dielectric layer on inner walls of the trenches; and   filling a conductive substance in the trenches.   
     
     
         30 . The method according to  claim 28 , wherein, between the step of forming the first bit line contacts and the step of forming the second bit line contacts, the method further comprises the step of:
 forming insulation spacers on sidewalls of the first bit line contacts.   
     
     
         31 . The method according to  claim 28 , wherein, between the step of forming the second bit line contacts and the step of forming the bit lines, the method further comprises the step of:
 forming insulation spacers on sidewalls of the second bit line contacts.   
     
     
         32 . The method according to  claim 28 , wherein, between the step of forming the bit lines and the step of forming the storage node contacts, the method further comprises the step of:
 forming insulation spacers on sidewalls of the bit lines.   
     
     
         33 . A semiconductor integrated circuit device comprising:
 first to third word lines extending along a first direction;   first to third bit lines extending along a second direction crossing the first direction;   a first memory cell formed in a space which is surrounded by the first word line, the second word line, the first bit line and the second bit line;   a second memory cell formed in a space which is surrounded by is the first word line, the second word line, the second bit line and the third bit line; and   a third memory cell formed in a space which is surrounded by the second word line, the third word line, the first bit line and the second bit line,   wherein the first memory cell and the third memory cell share the second word line, and   wherein the first memory cell and the second memory cell share the second bit line.   
     
     
         34 . The semiconductor integrated circuit device according to  claim 33 , wherein the first to third word lines are formed in such a way as to be buried into a semiconductor substrate.