Measurement apparatus

Abstract

Measurement apparatuses and methods are described. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance.

1 . A device, comprising:
 a first switch coupled between a measurement input and a node,   a second switch coupled between the node and a reference voltage,   a capacitance, a first terminal of the capacitance being coupled with the node, and   a measurement circuit, a terminal of said measurement circuit being coupled with a second terminal of said capacitance.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 at least one switchable further capacitance, wherein a first terminal of said at least one switchable further capacitance is coupled with a node between said second terminal of said capacitance and said measurement circuit.   
     
     
         3 . The apparatus of  claim 2 , wherein a second terminal of said at least one switchable further capacitance is switchably coupled with either a first reference voltage or a second reference voltage. 
     
     
         4 . The apparatus of  claim 2 , wherein said at least further switchable capacitance forms part of a capacitive digital-to-analog converter. 
     
     
         5 . The apparatus of  claim 2 , wherein said at least one switchable capacitance comprises a plurality of switchable further capacitances, said further capacitances having binary weighted capacitance values. 
     
     
         6 . The apparatus of  claim 2 , wherein said at least one switchable capacitance comprises a plurality of switchable further capacitances, said further capacitances having nominally equal values. 
     
     
         7 . The apparatus of  claim 1 , wherein said first switch and said second switch comprise transistors. 
     
     
         8 . The circuit of  claim 7 , wherein said first switch comprises a PMOS transistor and said second switch comprises an NMOS transistor. 
     
     
         9 . The apparatus of  claim 1 , wherein said first switch, said second switch and said capacitance are designed to tolerate a first voltage, and wherein said measurement circuit is designed to tolerate a second voltage smaller than said first voltage. 
     
     
         10 . The apparatus of  claim 1 , wherein said measurement circuit comprises at least one of a buffer, an integrator and an analog-to-digital converter. 
     
     
         11 . An apparatus, comprising:
 a first capacitance,   a voltage input coupled with a first terminal of said first capacitance via a first switch,   a reference voltage coupled to said first terminal of said first capacitance via a second switch,   a comparator, a first input of said comparator being coupled with a second terminal of said first capacitance,   a successive approximation register coupled with an output of said comparator, and   an array of second capacitances, a first terminal of each of said second capacitances being coupled with said first input of said comparator, and a second terminal of said second capacitances being selectively coupled with a further reference voltage.   
     
     
         12 . The apparatus of  claim 11 , wherein said second terminal of each of said second capacitances is selectively couplable either with said second reference voltage or a third reference voltage. 
     
     
         13 . The apparatus of  claim 11 , further comprising an array of switches, each switch of said array of switches being coupled with one of said second terminal of said second capacitances to perform said selective coupling. 
     
     
         14 . The apparatus of  claim 13 , wherein said array of switches is controlled by said successive approximation register. 
     
     
         15 . The apparatus of  claim 11 , wherein a second input of said comparator is coupled with a fourth reference voltage. 
     
     
         16 . The apparatus of  claim 11 , wherein said output of said comparator is coupled with said first input of said comparator via a switch. 
     
     
         17 . The apparatus of  claim 11 , wherein said first switch and said second switch are controllable such that when one of said first switch and said second switch is closed, the other one of said first switch and said second switch is open. 
     
     
         18 . The apparatus of  claim 11 , wherein said first switch and said second switch comprise at least one of a MOS transistor and a bipolar transistor. 
     
     
         19 . The apparatus of  claim 11 , wherein a capacitance value of said first capacitance is matched with capacitance values of said second capacitances. 
     
     
         20 . A method, comprising:
 alternately applying an input voltage and a reference voltage to a first input of a capacitor,   coupling a second terminal of said capacitor to a comparator, and   determining a bit value of an output signal based on an output of said comparator.   
     
     
         21 . The method of  claim 20 , further comprising:
 selectively coupling second terminals of further capacitances of a capacitance array either with a first reference voltage or a second reference voltage, first terminals of said further capacitances being coupled to said comparator.   
     
     
         22 . The method of  claim 21 , further comprising coupling an output of said comparator to an input of said comparator. 
     
     
         23 . The method of  claim 20 , wherein said input voltage is a voltage related to at least one of an automotive application and a safety application.