Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider

Abstract

A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

1 . A circuit, comprising:
 a delay unit, arranged to delay an input signal to generate a delayed signal; and   a latch, arranged to latch a delay control signal for controlling a delay amount of the delay unit, wherein the latch has an input terminal receiving the delay control signal, an output terminal coupled to the delay unit, and a control terminal receiving the delayed signal.   
     
     
         2 . A circuit, comprising:
 a delay unit, arranged to delay an input signal to generate a delayed signal; and   a latch, arranged to latch a delay control signal for controlling a delay amount of the delay unit, wherein the latch is controlled by the delayed signal so that the delay control signal is latched until the delayed signal triggers the latch.   
     
     
         3 . A pipeline delay circuit, comprising:
 a first delay unit, arranged to delay an input signal to generate a first delayed signal;   a second delay unit, arranged to delay the first delayed signal to generate a second delayed signal;   a first latch, having an input terminal receiving a delay control signal, an output terminal coupled to the first delay unit, and a control terminal receiving the first delayed signal; and   a second latch, having an input terminal coupled to the first latch, an output terminal coupled to the second delay unit, and a control terminal receiving the second delayed signal.   
     
     
         4 . A pipeline delay circuit, comprising:
 a first delay unit, arranged to delay an input signal to generate a first delayed signal;   a second delay unit, arranged to delay the first delayed signal to generate a second delayed signal;   a first latch, arranged to latch a delay control signal for controlling a delay amount of the pipeline delay circuit, wherein the first latch is controlled by the first delayed signal so that the delay control signal is latched until the first delayed signal triggers the first latch; and   a second latch, arranged to latch an output of the first latch or the delay control signal for controlling the delay amount of the pipeline delay circuit, wherein the second latch is controlled by the second delayed signal so that the output of the first latch or the delay control signal is latched until the second delayed signal triggers the second latch.