US2011255611A1PendingUtilityA1
Powered Patch Panel
Est. expirySep 28, 2025(expired)· nominal 20-yr term from priority
H04L 41/0213H04Q 2201/802H04L 43/0811H04Q 1/136H04M 19/00H04Q 1/03H04L 41/0803H04L 43/0817H04M 3/2254H04L 12/66
47
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Claims
Abstract
A powered patch panel (PPP) is disclosed that inserts power in mid-span regions of a network and provides fault-tolerance at the power supply level and the power-plane level. Information such as physical location, port status and policy enforcement information may be locally stored and utilized by a processor of the PPP to achieve network control and monitoring. A network management system and/or element management system may be provided to interface with processors of PPPs to achieve network monitoring, control and policy enforcement goals.
Claims
exact text as granted — not AI-modified1 . A powered patch panel comprising:
a memory that stores a control parameter; a plurality of ports, each port configured to support a network communication connection; a processor that configures at least one of the plurality of ports to selectively supply power to a powered device over the network communication connection based on the control parameter; first and second power input ports wherein power from the first power input port is combined with power from the second power input port into a single power source; and an analog-to-digital converter configured to monitor voltages of the first and second power input ports, wherein the processor is configured to determine a status of power supplied by the first and second power input ports based on the voltages monitored by the analog-to-digital converter.
2 . The powered patch panel of claim 1 , wherein the control parameter includes a current limit threshold, and the processor is configured to set a current limit for at least one of the plurality of ports based on the current limit threshold.
3 . The powered patch panel of claim 1 , further comprising:
a first power-plane and a second power-plane, the first and second power-planes being separately powered; a common circuit; a port circuit, the first power-plane configured to provide power to the common circuit and the second power-plane configured to provide power to the port circuit; and a register receiving power from the second power-plane, the common circuit communicating with the port circuit via a power isolator.
4 . The powered patch panel of claim 3 , wherein:
the first power input port comprises a positive terminal and a negative terminal; the second power input port comprises a positive terminal and a negative terminal; a first diode connects to either the positive or the negative terminal of the first power input port and a second diode connects to the corresponding terminal of the second power input port; the first and second diodes connect to a first node, and the positive or negative terminal of the first and second power input ports that are not connected to one of the first and second diodes is connected to a second node; and an in-line current manager connects to the first and second nodes to supply power to connected powered devices.
5 . The powered patch panel of claim 4 , wherein the in-line current manager is connected to independent power planes serving different portions of the powered patch panel through independent fuses, and the in-line current manager is connected to the connected powered devices through one of the fuses.
6 . The powered patch panel of claim 1 , further comprising:
a legacy detection support circuit; and a switch having a first position and a second position, wherein the legacy detection support circuit is configured to:
determine a characteristic of the powered device connected to the port based on a first current and a second current, and
measure the first current through the switch in the first position when a first test voltage is applied to the switch and measure the second current through the switch in the second position when a second test voltage is applied to the switch.
7 . The powered patch panel of claim 1 , further comprising a plurality of LEDs associated with the ports, at least one of the LEDs indicating at least one of a status of the port or a value of a stored control parameter.Join the waitlist — get patent alerts
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