Statically speculative compilation and execution

Abstract

A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls.

1 . A method, for use with a compiler architecture framework, comprising:
 performing a statically speculative compilation process to extract and use speculative static information;   encoding the speculative static information in an instruction set architecture of a processor; and   executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls.   
     
     
         2 . The method of  claim 1 , wherein executing comprises controlling at least some processor resources using the speculative static information encoded in the instruction set architecture. 
     
     
         3 . The method of  claim 1 ; wherein executing comprises operating processor-related mechanisms using the speculative static information encoded in the instruction set architecture. 
     
     
         4 . The method of  claim 1 , wherein the speculative static information comprises information about one or more of processor resource demands and information that contributes to determining processor resource demands. 
     
     
         5 . The method of  claim 1 , wherein executing includes static, static-dynamic, and dynamic execution paths. 
     
     
         6 . The method of  claim 1 , wherein the instruction set architecture comprises at least one of modified and additional instructions to propagate information through code and to store the information. 
     
     
         7 . The method of  claim 1 , wherein the compilation process exposes speculative static information to run time layers, and microarchitecture which performs the executing provides a mechanism to recover in case of static misprediction. 
     
     
         8 . The method of  claim 1 , wherein the compilation process extracts the speculative static information and performs compilation using the speculative static information to reduce power consumption in the processor. 
     
     
         9 . The method of  claim 1 , wherein the speculative static information comprises predictable static information and additional static information that is speculated based on the predictable static information. 
     
     
         10 . The method of  claim 1 , wherein executing is performed by microarchitecture that contains an extension, the extension supporting correctness of execution for performing the statically speculative compilation process. 
     
     
         11 . The method of  claim 10 , wherein the extension is comprised of at least one of hardware and software. 
     
     
         12 . The method of  claim 1 , wherein the compilation process performs static speculation, the static speculation determining information about execution of the computer program, the static speculation being controlled on an application-specific and adaptive basis and being managed with compile-time flags. 
     
     
         13 . The method of  claim 1 , wherein the compilation process determines processor performance and energy tradeoffs during compile-time and uses the tradeoffs during execution. 
     
     
         14 . The method of  claim 1 , wherein the compilation process performs design objective customization without changing the microarchitecture. 
     
     
         15 . The method of  claim 1 , wherein more information about processor resource usage is exposed with speculative static compilation than with predictable static information. 
     
     
         16 . The method of  claim 1 , wherein microarchitecture performs the executing, the microarchitecture using the speculative static information and dynamic information during execution. 
     
     
         17 . A silicon-based electronics system that uses the method of  claim 1 . 
     
     
         18 . A nano-electronics based electronic system that uses the method of  claim 1 . 
     
     
         19 . A processor framework comprising:
 a compiler which compiles a computer program, the compiler extracting speculative static information about the computer program during compilation; and   a tagless cache architecture that is accessed based on the extracted speculative static information.   
     
     
         20 . The processor framework of  claim 19 , wherein the speculative static information is used to register promote cache pointer information. 
     
     
         21 . The processor framework of  claim 19 , wherein the speculative static information is used to select cache pointers at run time. 
     
     
         22 . The processor framework of  claim 19 , further comprising at least one of:
 a scratchpad-memory based cache mechanism; and   an associative cache.   
     
     
         23 . The processor framework of  claim 22 , wherein the compiler selects which of plural cache accesses are mapped to which cache mechanisms based on the speculative static information. 
     
     
         24 . The processor framework of  claim 22 , wherein frequently used data with a low memory footprint is mapped to the scratchpad-memory based cache mechanism. 
     
     
         25 . The processor framework of  claim 19 , wherein associativity and block size in the tagless cache are logical and programmable. 
     
     
         26 . The processor framework of  claim 25 , wherein the compiler determines block sizes and associatively of a cache based on an analysis of the computer program. 
     
     
         27 . The processor framework of  claim 19 , further comprising a memory area for storing a cache pointer. 
     
     
         28 . The processor framework of  claim 19 , further comprising a Cache TLB (Translation Look-ahead Buffer) for capturing statically mispredicted cache pointers and other types of cache pointers. 
     
     
         29 . The processor framework of  claim 28 , wherein the Cache TLB comprises eight entries. 
     
     
         30 . The processor framework of  claim 19 , further comprising a microarchitecture for use in accessing the tagless cache, the microarchitecture accessing the tagless cache using at least one of static, static-dynamic, and dynamic cache access paths.