Attaching And Virtualizing Reconfigurable Logic Units To A Processor

Abstract

In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed.

1 . An apparatus comprising:
 a processor including a register to store a thread identifier and a pipeline having a plurality of stages to execute instructions out of order, the stages including a plurality of front-end stages, a plurality of execution units, and a plurality of back-end stages; and   a first reconfigurable logic unit including configurable logic elements coupled between a dispatch port and a writeback port of the pipeline, wherein the first reconfigurable logic unit is to perform a reconfigurable logic function indicated by a first instruction including a reconfigurable logic opcode, wherein first logic of the first reconfigurable logic unit is to determine whether the reconfigurable logic function is loaded based on the reconfigurable logic opcode and the thread identifier, and if so to provide a physical reconfigurable logic opcode and a configuration number associated with a configuration of the configurable logic elements, and otherwise to cause an exception.   
     
     
         2 . The apparatus of  claim 1 , further comprising a second reconfigurable logic unit coupled between a reorder buffer and a retirement unit of the back-end stages, wherein the second reconfigurable logic unit and the retirement unit are to execute operations in order on result data from the reorder buffer. 
     
     
         3 . The apparatus of  claim 2 , wherein the second reconfigurable logic unit is to perform a compression operation on matrix data of N×M form, wherein N and M are greater than 1. 
     
     
         4 . The apparatus of  claim 1 , wherein the first reconfigurable logic unit is to share a port of a plurality of dispatch ports and a port of a plurality of writeback ports with a first cache memory, a translation lookaside buffer (TLB), and a page miss handler (PMH), wherein the TLB is closer to the first cache memory than the PMH, and the PMH is closer to the first cache memory than the first reconfigurable logic unit. 
     
     
         5 . The apparatus of  claim 1 , wherein the reconfigurable logic opcode and the thread identifier are concatenated and provided to a content addressable memory to determine whether the reconfigurable logic function is loaded. 
     
     
         6 . The apparatus of  claim 1 , wherein the first instruction further includes a reconfigurable logic control block virtual address, and the first reconfigurable logic unit includes a mapping table to map a tuple of the first instruction to the physical reconfigurable logic opcode and the configuration number. 
     
     
         7 . The apparatus of  claim 1 , wherein the first reconfigurable logic unit is virtualized among a plurality of threads. 
     
     
         8 . The apparatus of  claim 1 , wherein a state of the first reconfigurable logic unit is saved on a context switch from a function responsive to a user-specified address and without an operating system execution handler. 
     
     
         9 . The apparatus of  claim 1 , wherein the first reconfigurable logic unit is to perform a pipelined load of a configuration of the configurable logic elements for an instruction to be performed while executing a second instruction in a different configuration of the configurable logic elements. 
     
     
         10 . An apparatus comprising:
 a general-purpose processor including a pipeline having a plurality of stages to execute instructions out-of-order, the stages including a plurality of front-end stages, a plurality of execution units, and a plurality of back-end stages; and   a reconfigurable logic unit coupled within a pipeline of the general-purpose processor unit including configurable logic elements, wherein the reconfigurable logic unit is to perform a reconfigurable logic function indicated by an instruction, the instruction including a reconfigurable logic control block virtual address and a reconfigurable logic opcode, and the reconfigurable logic unit including a mapping table to map a tuple of the instruction to a physical reconfigurable logic opcode and configuration number associated with a configuration of the configurable logic elements.   
     
     
         11 . The apparatus of  claim 10 , wherein the reconfigurable logic unit is to pre-compute a plurality of conditions affecting a multiway branch. 
     
     
         12 . The apparatus of  claim 11 , wherein the reconfigurable logic unit is to provide a result of the pre-computation to a branch predictor of the front-end units for use in a prediction. 
     
     
         13 . The apparatus of  claim 10 , wherein the reconfigurable logic unit is coupled between one of a plurality of dispatch ports of the front-end stages and one of a plurality of writeback ports of the back-end stages and is to share the port of the dispatch ports and the port of the writeback ports with at least one of the execution units. 
     
     
         14 . The apparatus of  claim 13 , wherein the reconfigurable logic unit is to share the port of the dispatch ports and the port of the writeback ports with a divider unit, wherein the reconfigurable logic unit and the divider unit each have a variable latency. 
     
     
         15 . The apparatus of  claim 10 , further comprising a second reconfigurable logic unit coupled between a first stage and a second stage of the back-end stages, wherein the second reconfigurable logic unit and the second stage are to execute operations in-order. 
     
     
         16 . The apparatus of  claim 10 , wherein the instruction includes a reconfigurable logic opcode concatenated with an identifier to identify a process executing on the apparatus associated with the instruction, wherein a plurality of processes are to share the reconfigurable logic unit. 
     
     
         17 . The apparatus of  claim 10 , wherein the reconfigurable logic unit includes a content addressable memory (CAM) to receive a concatenation of the reconfigurable logic opcode and a thread identifier and determine if a function associated with the instruction is loaded in the reconfigurable logic unit, wherein the reconfigurable logic unit is to signal an exception handler to obtain the function if it is not loaded. 
     
     
         18 . A method comprising:
 receiving a first instruction and a thread identifier in a reconfigurable logic unit from a processor coupled to the reconfigurable logic unit;   determining whether a reconfigurable logic function is loaded in the reconfigurable logic unit based on the reconfigurable logic opcode and the thread identifier; and   if so, providing a physical reconfigurable logic opcode and a configuration number associated with a configuration of configurable logic elements of the reconfigurable logic unit.   
     
     
         19 . The method of  claim 18 , further comprising if the reconfigurable logic function is not loaded, causing an exception. 
     
     
         20 . The method of  claim 19 , further comprising loading the reconfigurable logic function responsive to the exception via an exception handler.