Non-volatile memory device

Abstract

A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

1 . A semiconductor device, comprising:
 a tunnel insulating layer disposed on an active region of a substrate;   field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof;   a stacked structure disposed on the tunnel insulating layer; and   impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure, and   wherein the upper recess has a curved bottom surface.   
     
     
         2 . (canceled) 
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein the stacked structure includes a floating gate electrode, a blocking layer and a control gate electrode. 
     
     
         4 . The semiconductor device as claimed in  claim 3 , wherein the blocking layer extends continuously along upper surfaces of the field insulating patterns. 
     
     
         5 . The semiconductor device as claimed in  claim 4 , wherein the upper recess is filled with a conductive material of the control gate electrode. 
     
     
         6 - 22 . (canceled)