Semiconductor wafer and method for producing same

Abstract

A semiconductor wafer ( 12 ) with a thinned central portion ( 2 ) has a first side ( 3 ) and a second side ( 4 ) and at least one reinforcement structure for increasing the radial bending resistance of the semiconductor wafer ( 12 ). The reinforcement structure provides at least one passage ( 10 ) for a fluid flow between an inner face ( 9 ) of said one reinforcement structure towards an outer face ( 8 ) of the reinforcement structure. The passages ( 10 ) are manufactured in a z-direction coming from above the semiconductor wafer ( 12 ) in a direction which is essentially perpendicular to the surface, e.g. to the first side ( 3 ), of the semiconductor wafer ( 12 ).

1 . A semiconductor wafer ( 12 ) with a central portion ( 2 ) having a first side ( 3 ) and a second side ( 4 ) and at least one reinforcement structure, the reinforcement  5  structure providing at least one passage ( 10 ) for a fluid flow between an inner face ( 9 ) of said one reinforcement structure towards an outer face ( 8 ) of the reinforcement structure, the at least one passage ( 10 ) providing an elevated area ( 110 ) towards the outer face ( 8 ). 
     
     
         2 . The semiconductor wafer according to  claim 1 , wherein the elevated area ( 110 ) increases the radial bending resistance of the semiconductor wafer ( 12 ) 
     
     
         3 . The semiconductor wafer according to  claim 1 , wherein the passage ( 10 ) comprises an inner orifice ( 31 ′). 
     
     
         4 . The semiconductor wafer according to  claim 3 , wherein a height (h) of at least a portion of said passage ( 10 ) is larger than the thickness (d) of said thinned central portion ( 2 ). 
     
     
         5 . The semiconductor wafer according to  claim 1 , wherein said reinforcement structures comprise elevated areas ( 110 ) over the central portion  2 . 
     
     
         6 . The semiconductor wafer according to  claim 5 , wherein said passages ( 10 ) comprise slits ( 31 ) which separate at least two elevated areas ( 110 ) from each other. 
     
     
         7 . The semiconductor wafer according to  claim 5 , wherein said passages ( 10 ) comprise slits ( 31 ) which are provided within the elevated areas ( 110 ). 
     
     
         8 . The semiconductor wafer according to  claim 6 , wherein slits ( 31 ) are provided with a spatial orientation that includes a horizontal inclination angle σ (sigma) between the slit ( 31 ) and a horizontal direction of the wafer ( 12 ) at the location of the respective slit ( 31 ). 
     
     
         9 . The semiconductor wafer according to  claim 6 , wherein slits ( 31 ) are provided with a spatial orientation that provides a radial inclination angle φ (phi) between the slit ( 31 ) and a radial direction of  15  the wafer ( 12 ) at the location of the respective slit ( 31 ). 
     
     
         10 . The semiconductor wafer according to  claim 6 , wherein a spatial orientation of at least one slit ( 31 ) is provided such that there is no radial overlap of an inner orifice ( 31 ′) and a respective outer orifice of the slit ( 31 ). 
     
     
         11 . The semiconductor wafer according to  claim 1 , wherein said passage ( 10 ) comprises a ramp ( 60 ,  61 ) which is provided at the elevated area. 
     
     
         12 . The semiconductor wafer according to  claim 1 , wherein said first side ( 3 ) of said thinned central portion ( 2 ) comprises a front surface ( 11 ) of a standard semiconductor wafer ( 12 ). 
     
     
         13 . The semiconductor wafer according to  claim 1 , wherein said first side ( 3 ) comprises a plurality of integrated electronic circuits ( 15 ) or semiconductor devices. 
     
     
         14 . The semiconductor wafer according to  claim 1 , wherein said second side ( 4 ) of said thinned central portion ( 2 ) comprises a portion of a rear surface ( 16 ) of a standard semiconductor wafer ( 12 ). 
     
     
         15 . The semiconductor wafer according to  claim 1 , wherein said second side ( 4 ) of said thinned central portion ( 2 ) comprises a metallization structure ( 19 ) of a metallization layer ( 17 ). 
     
     
         16 . The semiconductor wafer according to  claim 1 , wherein said second side ( 4 ) of said central portion ( 2 ) comprises a plurality of metallization structures comprising insulation layers ( 18 ) between said metallization structures ( 19 ) and comprising through contacts through said insulation layers ( 18 ). 
     
     
         17 . The semiconductor wafer according to  claim 1 , wherein said second side ( 4 ) of said central portion ( 2 ) comprises a metallization structure ( 19 ) with contact bumps ( 20 ). 
     
     
         18 . The semiconductor wafer according to  claim 17 , wherein said contact bumps ( 20 ) comprise a seed layer ( 21 ) portion and at least a plated body of a copper or tin alloy coated with another metal, e.g. Au. Ag or Sn. 
     
     
         19 . The semiconductor wafer according to  claim 1 , wherein said first side ( 3 ) and said second side ( 4 ) of said thinned central portion ( 2 ) comprise recessed portions of a
 rear surface ( 16 ) and a front surface ( 11 ) of a standard semiconductor wafer ( 12 ), wherein each surface ( 11 ,  16 ) comprises a plurality of coordinated rectangular areas ( 13 ), wherein each coordinated area ( 13 ) comprises an integrated electronic circuit ( 15 ) or a semiconductor device.   
     
     
         20 . A method comprising
 providing a semiconductor wafer ( 40 ) comprising a front surface ( 11 ) and a rear surface ( 16 );   producing integrated electronic circuits ( 15 ) or semiconductor device structures at the front surface ( 11 );   providing at least one fluid passage ( 10 ) at a circumference on the front surface ( 11 ) extending radially between an outer face ( 8 ) of the wafer ( 40 ) and an inner face ( 9 ) of said wafer ( 40 ),   providing a recess at the rear surface ( 16 ) of the wafer ( 40 ) to provide a thinned central portion ( 2 ) having a first side ( 3 ) and a second side ( 4 ) surrounded by at least one reinforcement structure.   
     
     
         21 . Method according to  claim 20 , comprising the provision of holes for electrical connections between the front surface ( 11 ) and the rear surface ( 16 ) of the thinned central wafer portion. 
     
     
         22 . Method according to  claim 21 , comprising etching or laser ablating of the holes. 
     
     
         23 . Method according to  claim 20 , comprising the provision of a recess into the rear surface ( 16 ) of the wafer ( 40 ) and into the front surface ( 11 ) of the wafer ( 40 ) for providing a double recessed thinned central portion ( 29 ) having a first side ( 3 ) and a second side ( 4 ). 
     
     
         24 . Method according to  claim 20 , wherein providing said passage ( 10 ) comprises cutting of slits ( 31 ) by a dicing saw blade ( 32 ). 
     
     
         25 . The method according to  claim 24 , wherein a cutting depth (c) for said slits ( 31 ) is deeper than a thickness (d) of said thinned central portion ( 2 ). 
     
     
         26 . The method according to  claim 25 , wherein the cutting is done with a radial inclination. 
     
     
         27 . The method according to  claim 24 , wherein the cutting is done with a horizontal inclination. 
     
     
         28 . The method according to  claim 20 , wherein providing said passage ( 10 ) comprises dry etching. 
     
     
         29 . The method according to  claim 28 , wherein said etching comprises a RIE-plasma etching process. 
     
     
         30 . The method according to  claim 20 , wherein providing said passage ( 10 ) comprises wet etching. 
     
     
         31 . The method according to  claim 20 , wherein a deposition of a metal or carbon seed layer ( 21 ) for a metallization structure or a bump ( 20 ) plating structure is performed onto said second side ( 4 ) of said thinned central portion ( 2 ). 
     
     
         32 . The method according to  claim 31 , wherein said metal or carbon seed layer ( 21 ) is structured to said metallization structure and/or plated to said electrical bumps ( 34 ), by at least one of the steps of sprayed-on and spinning a photo-resist ( 35 ), of spraying-on developing liquids, of spraying-on etch liquids, of rinsing-on cleaning liquids, of spraying-on stripping liquid, of plating or of coating by electrolytic liquids under bypassing or escaping of excess liquids over said passage ( 10 ). 
     
     
         33 . The method according to  claim 31 , wherein said metal or carbon seed layer ( 19 ) is structured and plated to said metallization structure and/or said electrical bumps ( 20 ), comprising
 depositing a thin metal or carbon seed layer ( 21 ) to the second side ( 4 ) of the thinned central portion ( 2 );   spraying-on and spinning of a resist layer ( 35 ) under escaping of excess resist over said passage ( 10 );   drying the resist layer ( 35 );   structuring the dried layer by exposition through a mask;   developing the exposed resist layer ( 35 ) by spraying on developing liquid under escaping of excess resist and excess developing liquid over said passage ( 10 );   rinsing the structured resist layer ( 35 ) by spraying-on a rinsing liquid under escaping of excess rinsing liquid over said passage ( 10 );   hardening the developed resist structure to a plating mask ( 36 );   plating the uncoated resist free seed layer ( 19 ) to a metallization structure and/or to metallic bumps ( 34 ) in an electrochemical bath ( 37 ) by circulating the electrochemical liquid over the structured seed layer ( 19 ) and bypassing said liquid over said passage ( 10 );   stripping off the resist of said plating mask ( 36 ) from the second side ( 4 ) by spraying-on a stripping liquid under escaping of excess stripping liquid and stripped resist over said passage ( 10 );   cleaning the stripped structure by a cleaning liquid under escaping of excess cleaning liquid over said passage ( 10 );   wet etching remaining parts of the thin seed layer ( 19 ) by spraying-on of etch liquid under escaping of excess etch liquid over said passage ( 10 );   rinsing the etched structure by spraying-on a rinsing liquid under escaping of excess rinsing liquid over said passage ( 10 );   cleaning the second side with bumps by a cleaning liquid under escaping of excess cleaning liquid over said passage ( 10 ) and drying the semiconductor wafer ( 12 ).