Protocol including timing calibration between memory request and data transfer

Abstract

The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

1 . A method for controlling an integrated circuit memory device by a memory controller, the method comprising:
 sending a memory-access request to the memory device;   after sending the memory-access request, sending to the memory device a command that specifies performing a timing-calibration operation for a data transfer associated with the memory-access request; and   performing the data transfer for the memory-access request;   wherein the timing-calibration operation occurs between sending the memory-access request and the data transfer associated with the memory-access request.   
     
     
         2 . The method of  claim 1 , wherein the memory device is a non-volatile semiconductor memory. 
     
     
         3 . The method of  claim 2 , wherein the memory device is a flash memory. 
     
     
         4 . The method of  claim 1 , wherein the memory-access request is a write command, and wherein the method further comprises enabling a current source of an input receiver disposed on the memory device such that transferring the data includes receiving the data by the input receiver, and wherein the enabling of the current source and the receiving of the data are triggered at the memory device in response to the write command. 
     
     
         5 . The method of  claim 1 , wherein the memory-access request is a read command, and wherein the method further comprises enabling a current source of a transmitter disposed on the memory device such that transferring the data includes transmitting the data using the transmitter, and wherein the enabling of the current source and the transmitting of the data are triggered at the memory device in response to the read command. 
     
     
         6 . The method of  claim 1 ,
 wherein the memory-access request is sent through a first link between the memory controller and the memory device; and   wherein the data transfer takes place through a second link between the memory controller and the memory device.   
     
     
         7 . The method of  claim 6 , wherein the second link operates at a higher frequency than the first link. 
     
     
         8 . The method of  claim 7 , wherein communications across the second link have a lower voltage swing than communications across the first link. 
     
     
         9 . The method of  claim 6 ,
 wherein sending the memory-access request to the memory device through the first link involves sending the memory-access request through a multi-drop link which couples the memory controller to multiple memory devices; and   wherein performing the data transfer through the second link involves sending the data though a point-to-point link which couples the memory controller to a single memory device.   
     
     
         10 . The method of  claim 6 ,
 wherein sending the memory-access request to the memory device through the first link involves sending the memory-access request through a single-ended link; and   wherein performing the data transfer through the second link involves sending the data though a differential link.   
     
     
         11 . The method of  claim 6 , wherein the first link and the second link share a common communication channel. 
     
     
         12 . The method of  claim 1 , wherein the timing-calibration operation involves:
 locking a locked loop which provides a timing reference for communications on the second link; and/or   calibrating a phase relationship between a clock signal generated based on the timing reference and a data signal on the second link.   
     
     
         13 . The method of  claim 1 , wherein performing the timing-calibration operation involves:
 performing phase adjustments at the memory controller without associated phase adjustments at the memory device;   performing phase adjustments at the memory device without associated phase adjustments at the memory controller; or   performing phase adjustments at both the memory controller and the memory device.   
     
     
         14 . The method of  claim 1 , wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time. 
     
     
         15 . The method of  claim 14 , wherein the timing-calibration operation involves:
 setting a phase offset for the timing calibration to a minimum possible value; and   sweeping through an entire phase range and noting a fail-pass point and a pass-fail point for a data link between the memory controller and the memory device;   wherein the entire phase range includes multiple tBIT times.   
     
     
         16 . The method of  claim 1 , wherein the timing-calibration operation additionally involves enabling power sources for one or more of the following:
 a PLL;   a DLL;   a transmitter associated with the second link;   equalization circuitry associated with the second link;   a digital-to-analog converter associated with communications across the second link;   an analog-to-digital converter associated with communications across the second link;   a differential pair which comprises a communication channel for the second link; and   clocking circuitry in a clock tree for the memory device.   
     
     
         17 . The method of  claim 1 , wherein the method further comprises providing a bit-rate clock signal on a multi-drop link from the memory controller to multiple memory devices, wherein the bit-rate clock signal provides a frequency/phase reference for the second link. 
     
     
         18 . A memory system, comprising:
 a memory controller;   a memory device;   a first link to communicate memory-access requests from the memory controller to the memory device; and   a second link to communicate data associated with memory-access requests between the memory controller and the memory device;   wherein after a memory-access request is communicated, the memory system is to
 perform a timing-calibration operation for the second link, and 
 transfer data associated with the memory-access request using the second link, 
 wherein the timing-calibration operation occurs between communicating the memory-access request and transferring the data associated with the memory-access request. 
   
     
     
         19 . The memory system of  claim 18 , wherein the memory device is a non-volatile semiconductor memory. 
     
     
         20 . The memory system of  claim 19 , wherein the memory device is a flash memory. 
     
     
         21 . The memory system of  claim 18 , wherein when the memory-access request is a write command, the memory device is to enable a current source of an input receiver disposed on the memory device such that transferring the data includes receiving the data by the input receiver, and wherein enabling the current source and receiving the data are triggered at the memory device in response to the write command. 
     
     
         22 . The method of  claim 18 , wherein when the memory-access request is a read command, the memory device is to enable a current source of a transmitter disposed on the memory device such that transferring the data includes transmitting the data using the transmitter, and wherein the enabling of the current source and the transmitting of the data are triggered at the memory device in response to the read command. 
     
     
         23 . The memory system of  claim 18 , wherein the second link operates at a higher frequency than the first link. 
     
     
         24 . The memory system of  claim 23 , wherein communications across the second link have a lower voltage swing than communications across the first link. 
     
     
         25 . The memory system of  claim 18 ,
 wherein the first link is a multi-drop link which couples the memory controller to multiple memory devices; and   wherein the second link is a point-to-point link which couples the memory controller to a single memory device.   
     
     
         26 . The memory system of  claim 18 ,
 wherein the first link is a single-ended link; and   wherein the second link is a differential link.   
     
     
         27 . The memory system of  claim 18 , wherein while performing the timing-calibration operation, the memory system is to:
 lock a locked loop which provides a timing reference for communications on the second link; and/or   calibrate a phase relationship between a clock signal generated based on a timing reference and a data signal on the second link.   
     
     
         28 . The method of  claim 18 , wherein while performing the timing-calibration operation, the memory system is to:
 perform phase adjustments at the memory controller without associated phase adjustments at the memory device;   perform phase adjustments at the memory device without associated phase adjustments at the memory controller; or   perform phase adjustments at both the memory controller and the memory device.   
     
     
         29 . The memory system of  claim 18 , wherein while calibrating the phase relationship, the memory system is to perform multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time. 
     
     
         30 . The method of  claim 29 , wherein while calibrating the phase relationship, the memory system is to:
 set a phase offset for the timing calibration to a minimum possible value; and   sweep through an entire phase range and to determine a fail-pass point and a pass-fail point for a data link between the memory controller and the memory device;   wherein the entire phase range includes multiple tBIT times.   
     
     
         31 . The memory system of  claim 18 , further comprising power-source enablement circuitry, wherein in response to a memory-access request, the power-source enablement circuitry is to enable a power source for one or more of the following:
 a PLL;   a DLL;   a transmitter associated with the second link;   equalization circuitry associated with the second link;   a digital-to-analog converter associated with communications across the second link;   an analog-to-digital converter associated with communications across the second link;   a differential pair which comprises a communication channel for the second link; and   clocking circuitry in a clock tree for the memory device.   
     
     
         32 . The memory system of  claim 18 , further comprising a multi-drop link which provides a bit-rate clock signal from the memory controller to multiple memory devices, wherein the bit-rate clock signal provides a frequency/phase reference for the second link, thereby eliminating the need for a PLL or a DLL on the memory device. 
     
     
         33 . The memory system of  claim 18 , wherein the first link and the second link share a common communication channel. 
     
     
         34 . A memory controller, comprising:
 a first interface to communicate memory-access requests to a memory device;   a second interface to communicate data associated with the memory-access requests between the memory controller and the memory device;   wherein after sending a memory-access request, the memory controller is to:
 send to the memory device a command that specifies performing a timing-calibration operation through the first interface, and 
 transfer data associated with the memory-access request through the second interface, 
 wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request. 
   
     
     
         35 . The memory controller of  claim 34 , further comprising a bit-rate clock interface for a multi-drop link which provides a bit-rate clock signal from the memory controller to multiple memory devices, wherein the bit-rate clock signal provides a frequency/phase reference for the second interface, thereby eliminating the need for a PLL or a DLL on the memory device. 
     
     
         36 . The memory system of  claim 34 , wherein the first interface and the second interface share a common communication channel between the memory controller and the memory device. 
     
     
         37 . The memory system of  claim 34 , wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time. 
     
     
         38 . A memory, comprising:
 a first interface to receive memory-access requests from a memory controller; and   a second interface to communicate data associated with memory-access requests between the memory and the memory controller;   wherein in response to a memory-access request of the memory-access requests, the memory is to perform a timing-calibration operation for the second interface, wherein the timing-calibration operation is executed during a time interval that transpires between receiving the memory-access request and communicating the data associated with the memory-access request.   
     
     
         39 . The memory of  claim 38 , further comprising a bit-rate clock input to receive a bit-rate clock signal from the memory controller, wherein the bit-rate clock signal provides a frequency/phase reference for the second interface, thereby eliminating the need for a PLL or a DLL at the memory device. 
     
     
         40 . The memory of  claim 38 , wherein the first interface and the second interface share a common communication channel between the memory controller and the memory device. 
     
     
         41 . The memory of  claim 38 , wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time. 
     
     
         42 . A memory system, comprising:
 a memory controller;   a memory device;   a first link to communicate memory-access requests from the memory controller to the memory device;   a second link to communicate data associated with memory-access requests between the memory controller and the memory device;   wherein the first link and the second link share a common communication channel;   wherein after a memory-access request is communicated, the memory system is to
 perform a timing-calibration operation for the second link, and 
 transfer data associated with the memory-access request using the second link, 
 wherein the timing-calibration operation occurs between communicating the memory-access request and transferring the data associated with the memory-access request. 
   
     
     
         43 . The memory system of  claim 42 , wherein the timing-calibration operation involves multiple phase comparisons at different phase offsets which vary by at least one transmit bit (tBIT) time.