Delay circuit of semiconductor device

Abstract

A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.

1 . A delay circuit of a semiconductor device, comprising:
 a plurality of inverters configured to receive first and second voltages independent of variation of an external voltage; and   a plurality of delay units configured to receive a third voltage dependent on the variation of the external voltage,   wherein each of the delay units includes an NMOS transistor having a gate receiving the third voltage, and a source and a drain connected to an output node of one of the inverters.   
     
     
         2 . The delay circuit as recited in  claim 1 , further comprising a resistor connected between the inverters and the delay units. 
     
     
         3 . The delay circuit as recited in  claim 1 , wherein the inverters have a fixed delay time. 
     
     
         4 . The delay circuit as recited in  claim 1 , wherein the delay units have a delay time corresponding to the third voltage. 
     
     
         5 . The delay circuit as recited in  claim 1 , wherein the delay units have a propagation delay characteristic in which a delay time increases as the third voltage increases. 
     
     
         6 . The delay circuit as recited in  claim 5 , wherein the delay units include a MOS type capacitor. 
     
     
         7 . The delay circuit as recited in  claim 6 , wherein the MOS type capacitor includes an NMOS transistor having a gate receiving the third voltage, and a source and a drain connected to an output node of one of the inverters. 
     
     
         8 . The delay circuit as recited in  claim 5 , wherein a bulk terminal of the NMOS transistor is connected to the output node of one of the inverters. 
     
     
         9 . The delay circuit as recited in  claim 1 , wherein the third voltage has a voltage level substantially equal to the external voltage. 
     
     
         10 . The delay circuit as recited in  claim 1 , wherein the first voltage makes a power supply voltage of the inverters constant. 
     
     
         11 . The delay circuit as recited in  claim 1 , wherein the second voltage is a ground voltage.