Non-volatile memory with programmable capacitance

Abstract

Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.

1 . A memory unit, comprising:
 a substrate including a source region and a drain region;   an insulating layer over the substrate;   a gate contact layer over the substrate and between the source region and drain region, the gate contact layer electrically coupled to a voltage source;   a solid electrolyte layer between the insulating layer and the gate contact layer, the solid electrolyte layer has a capacitance that is controllable between at least two states;   a first electrode layer disposed between the solid electrolyte layer and the gate contact layer, the first electrode layer electrically coupled to the gate contact layer; and   a second electrode layer disposed between the solid electrolyte layer and the insulating layer, the second electrode layer electrically coupled to the voltage source.   
     
     
         2 . The memory unit according to  claim 1 , wherein the solid electrolyte layer capacitance is controlled by building or breaking metal dendrites within the solid electrolyte layer. 
     
     
         3 . The memory unit according to  claim 1 , wherein the second electrode layer comprises an electrochemically active metal and the first electrode layer comprises an electrochemically inert material. 
     
     
         4 . The memory unit according to  claim 1 , wherein the first electrode layer comprises an electrochemically active metal and the second electrode layer comprises an electrochemically inert material. 
     
     
         5 . The memory unit according to  claim 1 , wherein the solid electrolyte layer capacitance is controllable between at least two states with an application of a voltage of 500 millivolts or less across the first and second electrode layers. 
     
     
         6 . The memory unit according to  claim 1 , wherein the insulating layer, gate contact layer, and solid electrolyte layer form a gate stack. 
     
     
         7 . The memory unit according to  claim 1 , wherein the insulating layer, gate contact layer, first electrode layer, second electrode layer and solid electrolyte layer form a gate stack. 
     
     
         8 . The memory unit according to  claim 1 , wherein the solid electrolyte layer comprises a chalcogenide material. 
     
     
         9 . A method comprising:
 applying a programming voltage across a solid electrolyte layer that has a capacitance that is controllable between at least two states, the solid electrolyte layer between a gate oxide layer and a gate contact layer of a gate stack, the gate stack disposed on a substrate including a source region and a drain region, the gate oxide layer of the gate stack disposed adjacent to the source region and a drain region, wherein the programming voltage does not pass electrons through the gate oxide layer.   
     
     
         10 . The method according to  claim 9 , wherein the gate stack further comprises a first electrode layer disposed between the solid electrolyte layer and the gate contact layer, the first electrode layer electrically coupled to the gate contact layer, and a second electrode layer disposed between the solid electrolyte layer and the gate oxide layer, the second electrode layer electrically coupled to the voltage source. 
     
     
         11 . The method according to  claim 9 , wherein the applying step builds or breaks metal dendrites within the solid electrolyte layer. 
     
     
         12 . The method according to  claim 10 , wherein the second electrode layer comprises an electrochemically active metal and the first electrode layer comprises an electrochemically inert material. 
     
     
         13 . The method according to  claim 10 , wherein the first electrode layer comprises an electrochemically active metal and the second electrode layer comprises an electrochemically inert material. 
     
     
         14 . The method according to  claim 10 , wherein the solid electrolyte layer capacitance is controllable between at least two states with an application of a voltage of 500 millivolts or less across the first and second electrode layers. 
     
     
         15 . The method according to  claim 9 , further comprising applying a reading voltage across the gate stack and measuring a threshold voltage of the gate stack. 
     
     
         16 . A method comprising:
 providing a memory unit, comprising:
 a substrate including a source region and a drain region; 
 an insulating layer over the substrate; 
 a gate contact layer over the substrate and between the source region and drain region, the gate contact layer electrically coupled to a voltage source; 
 a solid electrolyte layer between the insulating layer and the gate contact layer, the solid electrolyte layer has a capacitance that is controllable between at least two states; 
 a first electrode layer disposed between the solid electrolyte layer and the gate contact layer, the first electrode layer electrically coupled to the gate contact layer; and 
 a second electrode layer disposed between the solid electrolyte layer and the insulating layer, the second electrode layer electrically coupled to the voltage source; 
   applying a programming voltage between a first electrode layer and a second electrode layer, wherein the programming voltage does not pass electrons through the gate oxide layer.   
     
     
         17 . The method according to  claim 16 , wherein the applying step builds or breaks metal dendrites within the solid electrolyte layer. 
     
     
         18 . The method according to  claim 16 , wherein the second electrode layer comprises an electrochemically active metal and the first electrode layer comprises an electrochemically inert material. 
     
     
         19 . The method according to  claim 16 , wherein the first electrode layer comprises an electrochemically active metal and the second electrode layer comprises an electrochemically inert material. 
     
     
         20 . The method according to  claim 16 , wherein the solid electrolyte layer capacitance is controllable between at least two states with an application of a voltage of 500 millivolts or less across the first and second electrode layers.