Row mask addressing

Abstract

Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.

1 . A method comprising:
 receiving a row address of a memory array, a column address of the memory array, and an amount of data to access in the memory array, the memory array having a row corresponding to the row address, the row having a plurality of memory cells;   generating a row mask address for accessing one or more memory cells of the row without accessing all the memory cells of the row; and   providing the row mask address to access memory cells of the row in response to generating the row mask address.   
     
     
         2 . The method of  claim 1 , wherein generating a row mask address comprises creating the row address mask substantially in real-time. 
     
     
         3 . The method of  claim 1 , wherein providing the row mask address to access memory cells comprises providing the row mask address to read from the accessed memory cells or to write to the accessed memory cells. 
     
     
         4 . The method of  claim 1 , wherein receiving a row address of a memory array, a column address of the memory array, and an amount of data to access in the memory array comprises receiving the row address, the column address, and a number of bits from a controller. 
     
     
         5 . An apparatus comprising:
 a mask generator to operatively access a portion of memory cells of a row of a memory array without accessing all the memory cells of the row, the mask generator including:
 an input to receive a request to access memory cells in the memory array; 
 a decoder to determine the portion of memory cells of the row to access in response to the request; and 
 a control unit to regulate signals to the memory array to access the memory cells of the row. 
   
     
     
         6 . The apparatus of  claim 5 , wherein the request comprises a row address, a column address, and an amount of data to access. 
     
     
         7 . The apparatus of  claim 5 , wherein the control unit is configured to provide a signal to one or more local access-lines assigned to the row to access the portion of memory cells such that the non-accessed memory cells of the row remain non-accessed while the portion of memory cells are accessed. 
     
     
         8 . The apparatus of  claim 7 , wherein the control unit is configured to block the signal such that the signal is not provided to the non-accessed memory cells. 
     
     
         9 . The apparatus of  claim 7 , wherein the control unit is configured to generate the signal only directed to the one or more access-lines. 
     
     
         10 . The apparatus of  claim 5 , wherein the mask generator is structured as a portion of a row address buffer or a row address decoder. 
     
     
         11 . A memory device comprising:
 an array of memory cells, the array having a row of memory cells;   a plurality of access-lines, each access-line coupled to one or more memory cells of the row to operatively access the one or more memory cells without accessing other memory cells of the row; and   a plurality of drivers to access the memory cells of the row, each driver corresponding to a different access-line to provide an access signal to its corresponding access-line.   
     
     
         12 . The memory device of  claim 11 , wherein the memory cells of the row are partitioned into groups, each group coupled to a different one of the access-lines, each group having the same number of memory cells. 
     
     
         13 . The memory device of  claim 11 , wherein the memory device comprises a decoder and the array disposed on a substrate, the decoder configured to receive a request and to select the access-lines to access a portion of the memory cells of the row without accessing all the memory cells of the row. 
     
     
         14 . The memory device of  claim 13 , wherein the decoder is configured to select one of the access-lines to access a portion of the memory cells of the row without accessing all the memory cells of the row. 
     
     
         15 . The memory device of  claim 14 , wherein the memory array comprises a plurality of rows, each row having a plurality of access-lines, each access-line of a respective row coupled to one or more memory cells of the respective row to operatively access the one or more memory cells without accessing other memory cells of the respective row, each of the plurality of access-lines of the respective rows operable to selectively access a sub-page of addressable space. 
     
     
         16 . The memory device of  claim 11 , wherein the array of memory cells includes a plurality of cell-plate ties, each cell-plate tie associated with a gap in the array such that a driver of the plurality of drivers is disposed in gap. 
     
     
         17 . The memory device of  claim 11 , wherein the array of memory cells includes a plurality of row line tie, each row line tie associated with a gap in the array such that a driver of the plurality of drivers is disposed in gap. 
     
     
         18 . The memory device of  claim 11 , wherein a plurality of drivers includes a boot node. 
     
     
         19 . The memory device of  claim 11 , wherein each driver includes an inverter.