US2011279462A1PendingUtilityA1

Method of and subsystem for graphics processing in a pc-level computing system

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Assignee: BAKALASH REUVENPriority: Nov 19, 2003Filed: May 5, 2011Published: Nov 17, 2011
Est. expiryNov 19, 2023(expired)· nominal 20-yr term from priority
Inventors:Reuven BakalashOffir RemezGigy Bar-OrEfi FogelAmir Shaham
G09G 5/363G06F 3/1438G06F 3/14G06T 15/005G06T 2200/28G06T 1/20G06F 9/505
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Claims

Abstract

A graphics processing subsystem for use in a computing system, including a plurality of GPUs operating according to time division mode of graphics parallelization. At least one of the GPUs is a display-designated GPU that is connectable to a screen for displaying images produced by the graphics processing subsystem, and at least one of the GPUs is a non-display-designated GPU. The subsystem includes a hardware hub having a router, and being located between a CPU of the computing system and the plurality of GPUs. For images to be generated and displayed on the screen, the router directs to the plurality of GPUs successively a stream of geometric data and graphics commands. The geometric data and graphics commands directed to a non-display-designated GPU are processed by the GPU into image pixel data associated with a frame, the image pixel data is then redirected to the router, the image pixel data is then redirected to the display-designated GPU, and the image pixel data is then displayed on the screen. Geometric data and graphics commands directed to the display-designated GPU are processed by the GPU into image pixel data associated with a frame, and the image pixel data is then displayed on the screen.

Claims

exact text as granted — not AI-modified
1 . A graphics processing subsystem of a computing system, comprising:
 a plurality of GPUs operating according to time division mode of graphics parallelization, wherein at least one of said GPUs is a display-designated GPU that is connectable to a screen for displaying images produced by said graphics processing subsystem, and at least one of said GPUs is a non-display-designated GPU, and   a hardware hub having a router, wherein said hardware hub is located between a CPU of the computing system and said plurality of GPUs,   wherein for images to be generated and displayed on said screen, said router directs to said plurality of GPUs successively a stream of geometric data and graphics commands, wherein:
 (i) geometric data and graphics commands directed to a non-display-designated GPU are processed by said GPU into image pixel data associated with a frame, said image pixel data is then redirected to the router, said image pixel data is then redirected to the display-designated GPU, and said image pixel data is then displayed on said screen; and 
 (ii) geometric data and graphics commands directed to the display-designated GPU are processed by said GPU into image pixel data associated with a frame, and said image pixel data is then displayed on said screen. 
   
     
     
         2 . The graphics subsystem of  claim 1 , wherein the hardware hub comprises a separate chip. 
     
     
         3 . The graphics subsystem of  claim 1 , wherein the hardware hub comprises a part of an I/O chipset. 
     
     
         4 . The graphics subsystem of  claim 1 , wherein said hardware hub is part of a CPU chip. 
     
     
         5 . The graphics subsystem of  claim 2 , wherein said hardware hub is interfaced with the computer system by a PCI express bus. 
     
     
         6 . The graphics subsystem of  claim 2 , wherein said hardware hub is interfaced with a CPU chip by a PCI express bus. 
     
     
         7 . The graphics subsystem of  claim 2 , wherein said hardware hub is interfaced with said plurality of GPUs by a PCI express bus. 
     
     
         8 . The graphics subsystem of  claim 3 , wherein said hardware hub is interfaced with said plurality of GPUs by a PCI express bus. 
     
     
         9 . The graphics subsystem of  claim 4 , wherein said hardware hub is interfaced with said plurality of GPUs by a PCI express bus. 
     
     
         10 . The graphics subsystem of  claim 1 , wherein said subsystem operates according to a plurality of modes of graphics parallelization. 
     
     
         11 . The graphics subsystem of  claim 10 , wherein said subsystem operates according to image division mode of graphics parallelization. 
     
     
         12 . The graphics subsystem of  claim 10 , wherein said subsystem operates according to object division mode of graphics parallelization. 
     
     
         13 . A method of providing a graphics subsystem comprising:
 a plurality of GPUs operating according to time division mode of graphics parallelization;   wherein at least one of said GPUs is a display-designated GPU that is connectable to a screen;   wherein at least one of said GPUs is a non-display-designated GPU, and   a hardware hub having a router, located between a CPU of the computing system and said plurality of GPUs;   said method comprising:
 interfacing the hardware hub with said CPU; 
 interfacing the hardware hub with said plurality of GPUs; and 
 for images to be generated and displayed on said screen:
 geometric data and graphics commands directed to a non-display-designated GPU are processed by said GPU into image pixel data associated with a frame, said image pixel data is then redirected to the router, said image pixel data is then redirected to the display-designated GPU, and said image pixel data is then displayed on said screen; and, 
 geometric data and graphics commands directed to the display-designated GPU are processed by said GPU into image pixel data associated with a frame, and said image pixel data is then displayed on said screen. 
 
   
     
     
         14 . The method of  claim 13 , wherein said hardware hub comprises a separate chip. 
     
     
         15 . The method of  claim 13 , wherein the hardware hub comprises a part of an I/O chipset in the computing system. 
     
     
         16 . The method of  claim 13 , wherein the hardware hub comprises a part of a CPU chip. 
     
     
         17 . The method of  claim 14 , wherein said hardware hub is interfaced with the computing system by a PCI express bus. 
     
     
         18 . The method of  claim 14 , wherein said hardware hub is interfaced with a CPU chip by a PCI express bus. 
     
     
         19 . The method of  claim 14 , wherein said hardware hub is interfaced with said plurality of GPUs by a PCI express bus. 
     
     
         20 . The method of  claim 15 , wherein said hardware hub is interfaced with said plurality of GPUs by a PCI express bus. 
     
     
         21 . The method of  claim 16 , wherein said hardware hub is interfaced with said plurality of GPUs by a PCI express bus. 
     
     
         22 . The method of  claim 13 , wherein said subsystem operates according to a plurality of modes of graphics parallelization. 
     
     
         23 . The method of  claim 22 , wherein said subsystem operates according to image division mode of graphics parallelization. 
     
     
         24 . The method of  claim 22 , wherein said subsystem operates according to object division mode of graphics parallelization.

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