Nonvolatile memory device, system comprising nonvolatile memory device, and read operation of nonvolatile memory device

Abstract

A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation. The control circuit is configured to control the first read operation and the second read operation to be performed in succession.

1 . A nonvolatile memory device, comprising:
 a memory cell array comprising a plurality of multi-level cells each configured to store a plurality of hard decision data bits;   a page buffer configured to sense whether each of the plurality of multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set a plurality of first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the plurality of multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation; and   a control circuit configured to control the first read operation and the second read operation to be performed in succession.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein the page buffer comprises:
 a plurality of sensing latches configured to sense whether each of the plurality of multi-level cells is in the on-cell state or the off-cell state in the first read operation;   a plurality of first soft decision data latches configured to store the first soft decision data bits; and   a plurality of pre-charge circuits configured to selectively supply a pre-charge voltage to a plurality of bitlines connected to the multi-level cells according to the first soft decision data bits, in a third read operation;   wherein each of the plurality of sensing latches senses whether at least one of the plurality of multi-level cells that was sensed as an off-cell in the first read operation assumes the on-cell state or the off-cell state during the third read operation in response to a third read voltage applied to the selected wordline.   
     
     
         3 . The nonvolatile memory device of  claim 2 , wherein the first read voltage and the third read voltage have the same magnitude. 
     
     
         4 . The nonvolatile memory device of  claim 2 , wherein each of the plurality of sensing latches senses one of the hard decision data bits while the pre-charge voltage is applied to corresponding bitlines and the second read voltage is applied to the selected wordline. 
     
     
         5 . The nonvolatile memory device of  claim 2 , wherein the page buffer transfers a plurality of sensed hard decision data bits to a plurality of cache latches and outputs one of a plurality of sensed hard decision data bits from each of the plurality of cache latches during an output operation, senses whether each of the plurality of multi-level cells assumes an on-cell state or an off-cell state in response to a fourth read voltage applied to the selected wordline during a fourth read operation, and sets second soft decision data bits based on the fourth read operation; and
 wherein the output operation and the fourth read operation are performed concurrently.   
     
     
         6 . The nonvolatile memory device of  claim 2 , wherein the multi-level cells are flash memory cells each configured to store two or more bits. 
     
     
         7 . A method of performing a read operation in a nonvolatile memory device comprising a plurality of multi-level cells each storing a plurality of hard decision data bits, the method comprising:
 performing a first read operation to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline;   setting first soft decision data bits according to the first read operation; and   performing a second read operation to sense the hard decision data bits stored in the multi-level cells by applying a second read voltage to the selected wordline, wherein the first read operation and the second read operation are performed in succession.   
     
     
         8 . The method of  claim 7 , wherein the first read operation comprises:
 sensing bits stored in the multi-level cells according to whether the multi-level cells assume the on-cell state or the off-cell state in response to the first read voltage applied to the selected wordline; and   storing the sensed bits as the first soft decision data bits.   
     
     
         9 . The method of  claim 8 , further comprising:
 performing a third read operation by applying a third read voltage to the selected wordline while selectively supplying a pre-charge voltage to a plurality of bitlines connected to the multi-level cells according to the first soft decision data bits; and   determining whether at least one of the multi-level cells that assumes the off-cell state in the first read operation assumes the on-cell state in the third read operation.   
     
     
         10 . The method of  claim 9 , wherein the first read voltage and the third read voltage have the same magnitude. 
     
     
         11 . The method of  claim 9 , wherein the second read operation comprises:
 selectively supplying the pre-charge voltage to the plurality of bitlines according to bits sensed in the third read operation; and   sensing one of the hard decision data bits using the pre-charge voltage and the second read voltage.   
     
     
         12 . The method of  claim 9 , further comprising:
 storing the sensed hard decision data bits to the cache latches and outputting one of the plurality of stored hard decision data bits from each of the plurality of cache latches;   performing a fourth read operation to sense whether each of the plurality of multi-level cells assumes the on-cell state or the off-cell state in response to a fourth read voltage applied to the selected wordline; and   setting second soft decision data bits according to the fourth read operation;   wherein the output operation and the fourth read operation are performed concurrently.   
     
     
         13 . The method of  claim 12 , wherein the multi-level cells comprise flash memory cells arranged in a NAND flash configuration. 
     
     
         14 . An electronic data storage apparatus, comprising:
 a nonvolatile memory device comprising a plurality of multi-level cells; and   a controller configured to control the apparatus to perform a read operation on the nonvolatile memory device by applying a first read voltage to a selected wordline connected to a selected multi-level cell in a first read operation, detecting whether the selected multi-level cell has an on-cell state or an off-cell state in the first read operation, and selectively applying a pre-charge voltage to a selected bitline connected to the selected multi-level cell while applying a second read voltage to the selected wordline in a second read operation;   wherein the pre-charge voltage is applied to the selected bitline in the second read operation based on whether the selected multi-level cell is in the on-cell state or the off-cell state in the first read operation.   
     
     
         15 . The apparatus of  claim 14 , wherein the pre-charge voltage is applied to the selected bitline in the second read operation upon determining that the selected multi-level cell is in the on-cell state in the first read operation. 
     
     
         16 . The apparatus of  claim 14 , further comprising:
 a page buffer that senses whether the selected multi-level cell is in the on-cell state or the off-cell state in the first read operation, sets a first soft decision data bit based on the detection, and senses a hard decision data bit stored in the selected multi-level cell in response to a third read voltage applied to the selected wordline during a third read operation;   wherein the first read operation, the second read operation, and the third read operation are performed in succession.   
     
     
         17 . The apparatus of  claim 16 , further comprising:
 an error correction circuit configured to perform error detection and error correction on a plurality of hard decision data bits read output from the nonvolatile memory device.   
     
     
         18 . The apparatus of  claim 16 , wherein the page buffer comprises:
 a plurality of sensing latches that sense whether the plurality of multi-level cells are in the on-cell state or the off-cell state in the first read operation;   a plurality of first soft decision data latches that set and store a plurality of first soft decision data bits corresponding to the plurality of multi-level cells; and   a plurality of pre-charge circuits each selectively supplying a pre-charge voltage to a corresponding bitline according to the plurality of first soft decision data bits.   
     
     
         19 . The apparatus of  claim 17 , wherein the first read voltage and the second read voltage have the same magnitude. 
     
     
         20 . The apparatus of  claim 14 , further comprising a host interface configured to interface between the nonvolatile memory device and a host system.