Semiconductor integrated circuit for generating clock signals

Abstract

A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference dock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.

1 . A voltage measuring apparatus for a semiconductor integrated circuit comprising:
 a first delay unit configured to delay a reference dock signal in a first noise region;   a second delay unit configured to delay the reference dock signal in a second noise region; and   an analysis unit configured to analyze a difference in voltage level between the noise regions according to signals transmitted from the first delay unit and the second delay unit.   
     
     
         2 . The voltage measuring apparatus of  claim 1 ,
 wherein the first delay unit and the second delay unit are supplied with the same power source voltage, and wherein the first noise region is less susceptible to noise than the second noise region.   
     
     
         3 . The voltage measuring apparatus of  claim 1 ,
 wherein the analysis unit comprises:   a phase comparison unit configured to compare the phase of an output dock signal from the first delay unit with the phase of an output dock signal from the second delay unit, and outputs a phase comparison signal indicative of the difference in power source voltage levels for the first and second noise regions based on the comparison.   
     
     
         4 . The voltage measuring apparatus of  claim 3 , wherein the analysis unit further comprises:
 a storage unit configured to store an electric charge associated with the phase comparison signal, when a reset signal is disabled; and   a conversion unit configured to convert the electric charge stored in the storage unit into a digital code signal.   
     
     
         5 . The voltage measuring apparatus of  claim 3 ,
 wherein the phase comparison unit is configured to implement the phase comparison signal as an up signal and a down signal in a toggle manner,   wherein the phase comparison unit is configured to increase the pulse width of the up signal when the comparison indicates the power source voltage level for the second noise region is higher than the power source voltage level of the first noise region, and increase the pulse width of the down signal when the comparison indicates the power source voltage level of the first noise region is higher than the power source voltage level of the second noise region.   
     
     
         6 . The voltage measuring apparatus of  claim 3 ,
 wherein the conversion unit is configured to enable the reset signal to reset the electric charge stored in the storage unit, when the conversion operation is completed.   
     
     
         7 . The voltage measuring apparatus of claim further comprising:
 a clock generation unit configured to generate the reference clock signal from an external clock signal.   
     
     
         8 . The voltage measuring apparatus of  claim 7 ,
 wherein the dock generation unit is a DLL (Delayed Locked Loop) circuit or a PLL (Phase Locked Loop) circuit.   
     
     
         9 . A method of measuring a voltage for a semiconductor integrated circuit, the method comprising:
 delaying a reference dock signal in a first noise region and a second noise region to generate a first delayed clock signal and a second delayed clock signal;   comparing the phase of the first delayed clock signal with the phase of the second delayed clock signal, individually; and   converting the phase comparison result of the first delayed clock signal and the second delayed clock signal into a digital code as an analysis signal.   
     
     
         10 . The method of  claim 9 ,
 wherein the first noise region and the second noise region are supplied with the same power source voltage, and the first noise region is less susceptible to noise than the second noise region.   
     
     
         11 . The method of  claim 9 ,
 wherein the comparing of the phases further comprises, when a reset signal is disabled, storing an electric charge from the phase comparison signal.   
     
     
         12 . The method of  claim 9 ,
 wherein the comparing of the phases generates the phase comparison signal as an up signal and a down signal in a toggle manner, such that as a power source voltage level of the second noise region exceeds a power source voltage of the first noise region, the pulse width of the up signal increases, and as the power source voltage level of the first noise region exceeds the power source voltage level of the second noise region, the pulse width of the down signal increases.   
     
     
         13 . The method of  claim 11 ,
 wherein, when the conversion operation is completed, the converting enables the reset signal to reset the electric charge stored from the phase comparison signal.   
     
     
         14 . The method of  claim 9 , further comprising, before the generating of the first and second delayed dock signals:
 generating the reference dock having more advanced phase than the external dock for a predetermined time.