Method of forming a unique number

Abstract

A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

1 . A method of forming a unique number comprising:
 increasing a power supply voltage input to a first transistor and a second transistor in each memory cell of a plurality of memory cells from ground to an operating level, each memory cell assuming a logic state in response to the power supply voltage input to the first transistor and the second transistor being increased from ground to the operating level; and   forming the unique number from a number of logic states held by a number of memory cells of the plurality of memory cells, each of the number of logic states being a logic state that was assumed in response to the power supply voltage input to the first transistor and the second transistor being increased from ground to the operating level.   
     
     
         2 . The method of  claim 1  wherein all voltages on all nodes within each memory cell are equal to ground before the power supply voltage input to the first transistor and the second transistor is increased from ground to the operating voltage. 
     
     
         3 . The method of  claim 2  wherein no logic state is written into any memory cell after a logic state has been assumed in response to the power supply voltage input to the first transistor and the second transistor being increased from ground to the operating level, and before the number of logic states are used to form the unique number. 
     
     
         4 . The method of  claim 2  wherein the plurality of memory cells are arranged in an array that includes a plurality of rows and a plurality of columns. 
     
     
         5 . The method of  claim 4  and further comprising reading the number of logic states from the number of memory cells before the unique number is formed. 
     
     
         6 . The method of  claim 5  wherein a logic state is read from each memory cell in the array. 
     
     
         7 . The method of  claim 6  wherein logic states read from a first row, a last row, a first column, and a last column of the array are dropped before forming the unique number. 
     
     
         8 . The method of  claim 2  wherein each memory cell assumes a non-random logic state in response to the power supply voltage input to the first transistor and the second transistor being increased from ground to the operating level. 
     
     
         9 . The method of  claim 2  wherein more than 20 and less than all memory cells assume a non-random logic state in response to the power supply voltage input to the first transistor and the second transistor being increased from ground to the operating level. 
     
     
         10 . The method of  claim 4  and further comprising grounding all word lines and all bit lines that are connected to a decoding circuit and the plurality of memory cells for a predetermined time before the power supply voltage input to the to the first transistor and the second transistor is increased from ground to the operating level. 
     
     
         11 . The method of  claim 10  wherein the predetermined time is measured by a timer. 
     
     
         12 . The method of  claim 10  wherein each word line is connected to a row of memory cells, and each bit line is connected to a column of memory cells. 
     
     
         13 . The method of  claim 12  wherein an access transistor in a memory cell is connected to a word line and a bit line. 
     
     
         14 . The method of  claim 13  wherein each memory cell is a static random access memory cell. 
     
     
         15 . A method, comprising:
 detecting the presence of power at a control circuit in a semiconductor;   initiating a timer with an expiration on the semiconductor;   outputting control signals thereby causing nodes in an array of cells in the semiconductor to discharge;   applying power to the array of cells upon timer expiration; and   reading the states assumed by a plurality of cells in the array of cells, each of the plurality of cells assuming one of two logic states depending on variations of the semiconductor caused by the fabrication process.   
     
     
         16 . The method of  claim 15 , further comprising generating an identification number based at least in part on the states read from the plurality of cells. 
     
     
         17 . The method of  claim 16 , further comprising programming the identification number into a read-only memory. 
     
     
         18 . The method of  claim 17 , further comprising: following programming,
 outputting control signals causing nodes in the array of cells in the semiconductor to discharge;   reapplying power to the array of cells; and   reading the states assumed by the plurality of cells in the array of cells.   
     
     
         19 . The method of  claim 15 , further comprising performing each of the steps within the semiconductor. 
     
     
         20 . The method of  claim 18 , further comprising performing each of the steps within the semiconductor. 
     
     
         21 . A method, comprising:
 utilizing fabrication variations of a semiconductor for creating a plurality of cells assuming one of two logic states, each cell having nodes;   discharging nodes of at least one of the plurality of cells;   applying power to the cells; and   reading the states assumed by at least a subset of cells of the plurality of the cells.   
     
     
         22 . The method of  claim 21 , the plurality of cells being an array of cells. 
     
     
         23 . The method of  claim 21 , further comprising:
 generating an identification number based at least in part on states assumed by the subset of cells; and   programming the identification number into a read-only memory.   
     
     
         24 . The method of  claim 23 , further comprising: following the programming,
 discharging nodes of at least one of the plurality of cells;   reapplying power to the cells; and   reading the states assumed by at least the subset of cells.   
     
     
         25 . The method of  claim 22 , the reading of the states assumed by the subset of cells not including reading a first and a last row and a first and a last column of the array of cells. 
     
     
         26 . The method of  claim 22 , the array of cells being static random access memory (SRAM) cells in which the cells are read but not written. 
     
     
         27 . The method of  claim 24 , further comprising identifying cells of the plurality of cells assuming a non-random state upon reapplying power to the cells. 
     
     
         28 . The method of  claim 27 , further comprising:
 selecting a portion of the identification number relating to cells assuming a non-random state; and   identifying the semiconductor using the portion of the identification number.   
     
     
         29 . The method of  claim 24 , further comprising performing each of the steps within the semiconductor. 
     
     
         30 . The method of  claim 21 , further comprising performing each of the steps within the semiconductor. 
     
     
         31 . A method, comprising:
 utilizing fabrication variations of a semiconductor for creating a plurality of cells assuming one of two logic states, each cell having nodes;   applying power to the plurality of cells;   reading the states assumed by a subset of cells of the plurality of cells; and   generating an identification number based at least in part on states assumed by the subset of cells.   
     
     
         32 . The method of  claim 31 , the plurality of cells being an array of cells, and the reading of the states assumed by the subset of cells not including reading a first and a last row and a first and a last column of the array. 
     
     
         33 . The method of  claim 32 , the array of cells being static random access memory (SRAM) in which the cells are read but not written. 
     
     
         34 . The method of  claim 31 , further comprising:
 programming the identification number into read-only memory;   
     
     
         35 . The method of  claim 34 , further comprising: following the programming,
 discharging nodes of cells in the plurality of cells;   reapplying power to the array of cells; and   reading the states assumed by the subset of cells.   
     
     
         36 . The method of  claim 35 , further comprising identifying cells of the plurality of cells assuming a non-random state when power is applied to the cells. 
     
     
         37 . The method of  claim 36 , further comprising:
 selecting a portion of the identification number relating to cells assuming a non-random state; and   identifying the semiconductor using the portion of the identification number.