Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure

Abstract

The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.

1 . A computer-implemented method for optimizing a test flow within an ATE (Automated Test Equipment) station for testing at least one semiconductor chip, the test flow listing a plurality of test blocks or tests in a sequence according to which the plurality of test blocks or tests are run, a test block including one or more tests that need to be run together in a specific sequence, the method comprising:
 determining one or more of: a test failure model, a test block duration and a yield model, the test failure model determining an order or sequence of the test blocks, the test block duration describing how long it takes for the ATE station to complete all tests in a test block, the yield model describing whether a semiconductor chip is defective or not;   scheduling the test flow based on said one or more of: the test failure model, the test block duration and the yield model; and   automatically conducting tests in the plurality of test blocks on at least one wafer or at least one semiconductor chip according to the scheduled test flow.   
     
     
         2 . The computer-implemented method according to  claim 1  further comprises:
 receiving one or more of: a test process structure, a test process constraint and a stopping criterion, the test process structure including a list of the tests performed on the wafer and the semiconductor chip, characteristics of the tests and individual durations of the tests, the test process constraint describing relationships between the tests and the test stopping criterion describing when one or more of the tests will stop. 
 
     
     
         3 . The computer-implemented method according to  claim 2 , wherein the test failure model comprises: an independent failure model and a dependent failure model, the independent failure model representing that a success or failure of a test or test block does not depend on a success or failure of any other test or test block run before or after in the test flow, the dependent failure model representing that the success or failure of a test depends on a success or failure of another test or test block run before or after in the test flow. 
     
     
         4 . The computer-implemented method according to  claim 3 , wherein the independent failure model comprises steps of:
 obtaining history data from a storage device;   computing a value N b   f  representing a number of semiconductor chips failed within each test block b based on the history data;   computing the test block duration t b  of each test block b based on the history data; and   reordering the plurality of test blocks in a decreasing order of a ratio   
       
         
           
             
               
                 
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         5 . The computer-implemented method according to  claim 4 , wherein the independent failure model further comprises steps of:
 updating the history data after conducting the tests; and   periodically re-running the computing the value N b   f , the computing the duration based on the updated history data and the reordering.   
     
     
         6 . The computer-implemented method according to  claim 3 , wherein the dependant failure model comprises steps of:
 obtaining history data from a storage device;   for each test block b, computing a value N b   f (i) based on the history data, the N b   f (i) representing a number of semiconductor chips failed by the test block b given that the semiconductor chips passed all test blocks 1, i, the i representing a test block number which is less than b;   computing the test block duration t b  of each test block b based on the history data; and   selecting a test block with a largest   
       
         
           
             
               
                 
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       to be scheduled as an ith test block in the test flow. 
     
     
         7 . The computer-implemented method according to  claim 6 , wherein the dependent failure model further comprises steps of:
 updating the history data after conducting the tests; and   periodically re-running the computing the value N b   f (i), the computing the duration based on the updated history data and the selecting.   
     
     
         8 . The computer-implemented method according to  claim 6 , wherein the history data include test failure dependency information including a conditional probability of a test resulting in a failure given that a previous test resulted in a pass. 
     
     
         9 . The computer-implemented method according to  claim 3 , further comprising:
 enforcing the test process constraint when scheduling the test flow based on the independent and dependent failure models.   
     
     
         10 . The computer-implemented method according to  claim 9 , wherein the test process constraint includes that the particular test blocks cannot be reordered. 
     
     
         11 . The computer-implemented method according to  claim 1 , wherein the scheduling is different for each different collection of wafers or for each different spatial location of semiconductor chips on the wafers. 
     
     
         12 . A computer-implemented system for optimizing a test flow within an ATE (Automated Test Equipment) station for testing at least one semiconductor chip, the test flow listing a plurality of test blocks or tests in a sequence according to which the plurality of test blocks or tests are run, a test block including one or more tests that need to be run together in a specific sequence, the system comprising:
 a memory device; and   a processor unit in communication with the memory device, the processor unit performs steps of   determining one or more of: a test failure model, a test block duration and a yield model, the test failure model determining an order or sequence of the test blocks, the test block duration describing how long it takes for the ATE station to complete all tests in a test block, the yield model describing whether a semiconductor chip is defective or not;   scheduling the test flow based on said one or more of the test failure model, the test block duration and the yield model; and   automatically conducting tests in the plurality of test blocks on at least one wafer or at least one semiconductor chip according to the scheduled test flow.   
     
     
         13 . The computer-implemented system according to  claim 12 , wherein the processor unit further performs a step of:
 receiving one or more of: a test process structure, a test process constraint and a stopping criterion, the test process structure including a list of the tests performed on the wafer and the semiconductor chip, characteristics of the tests and individual durations of the tests, the test process constraint describing relationships between the tests and the test stopping criterion describing when one or more of the tests will stop.   
     
     
         14 . The computer-implemented system according to  claim 13 , wherein the test failure model comprises: an independent failure model and a dependent failure model, the independent failure model representing that a success or failure of a test or test block does not depend on a success or failure of any other test or test block run before or after in the test flow, the dependent failure model representing that the success or failure of a test depends on a success or failure of another test or test block run before or after in the test flow. 
     
     
         15 . The computer-implemented system according to  claim 14 , wherein the independent failure model comprises steps of:
 obtaining history data from a storage device;   computing a value N b   f  representing a number of semiconductor chips failed within each test block b based on the history data;   computing the test block duration t b  of each test block b based on the history data; and   reordering the plurality of test blocks in a decreasing order of a ratio   
       
         
           
             
               
                 
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         16 . The computer-implemented system according to  claim 15 , wherein the independent failure model further comprises steps of:
 updating the history data after conducting the tests; and   periodically re-running the computing the value N b   f , the computing the duration based on the updated history data and the reordering.   
     
     
         17 . The computer-implemented system according to  claim 14 , wherein the dependant failure model comprises steps of:
 obtaining history data from a storage device;   for each test block b, computing a value N b   f (i) based on the history data, the N b   f (i) representing a number of semiconductor chips failed by the test block b given that the semiconductor chips passed all test blocks 1, . . . , i, the i representing a test block number which is less than b;   computing the test block duration t b  of each test block b based on the history data; and   selecting a test block with a largest   
       
         
           
             
               
                 
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       to be scheduled as an ith test block in the test flow. 
     
     
         18 . The computer-implemented system according to  claim 17 , wherein the dependent failure model further comprises steps of:
 updating the history data after conducting the tests; and   periodically re-running the computing N b   f (i), the computing the duration based on the updated history data and the selecting.   
     
     
         19 . The computer-implemented system according to  claim 17 , wherein the history data include test failure dependency information including a conditional probability of a test resulting in a failure given that a previous test resulted in a pass. 
     
     
         20 . The computer-implemented system according to  claim 14 , wherein the processor unit further performs a step of:
 enforcing the test process constraint when scheduling the test flow based on the independent and dependent failure models.   
     
     
         21 . The computer-implemented system according to  claim 13 , wherein the constraint includes that the particular test blocks cannot be reordered. 
     
     
         22 . A computer program product for optimizing a test flow within each ATE (Automated Test Equipment), the test flow including a plurality of test blocks, a test block including a plurality of tests, the computer program product comprising: a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising steps of:
 determining one or more of a test failure model, a test block duration and a yield model, the test failure model determining an order or sequence of the test blocks, the test block duration describing how long it takes for the ATE station to complete all tests in a test block, the yield model describing whether a semiconductor chip is defective or not;   scheduling the test flow based on said one or more of: the test failure model, the test block duration and the yield model; and   automatically conducting tests in the plurality of test blocks on at least one wafer or at least one semiconductor chip according to the scheduled test flow.   
     
     
         23 . The computer program product according to  claim 22 , wherein the test failure model comprises: an independent failure model and a dependent failure model, the independent failure model representing that a success or failure of a test or test block does not depend on a success or failure of any other test or test block run before or after in the test flow, the dependent failure model representing that the success or failure of a test depends on a success or failure of another test or test block run before or after in the test flow. 
     
     
         24 . A computer-implemented method for optimizing a test schedule of programming codes, the test schedule listing a plurality of test blocks or tests in a sequence according to which the plurality of test blocks or tests are run, a test block including one or more tests that need to be run together in a specific sequence, the method comprising:
 determining one or more of: an independent failure model and a dependent failure model, the independent failure model representing that a success or failure of a first test does not depend on a success or failure of a second test run before or after the first test, the dependent failure model representing that the success or failure of the first test depends on a success or failure of the second test run before or after the first test;   ordering the plurality of the test blocks according to the determined failure model; and   testing the programming codes according to the order.   
     
     
         25 . The computer-implemented method according to  claim 24 , wherein the independent failure model comprises steps of:
 obtaining history data from a storage device;   computing a value N b   f  representing a number of semiconductor chips failed within each test block b based on the history data;   computing the test block duration t b  of each test block b based on the history data; and   reordering the plurality of test blocks in a decreasing order of a ratio   
       
         
           
             
               
                 
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       wherein the dependant failure model comprises steps of:
 obtaining history data from a storage device; 
 for each test block b, computing a value N b   f (i) based on the history data, the N b   f (i) representing a number of semiconductor chips failed by the test block b given that the semiconductor chips passed all test blocks 1, . . . , i, the i representing a test block number which is less than b; 
 computing the test block duration t b  of each test block b based on the history data; and 
 selecting a test block with a largest 
 
       
         
           
             
               
                 
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       to be scheduled as an ith test block in the test flow.