Memory system and method having point-to-point link

Abstract

A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.

1 . A memory system, comprising:
 a controller for generating a control signal; and   a memory module, the memory module comprising:   a primary memory, directly coupled to the controller external to the memory module, for receiving the control signal from the controller using a first signal transfer protocol; and   a secondary memory coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory using a second signal transfer protocol, and communicating with the controller through the primary memory;   wherein the second signal transfer protocol is an at least partially serialized version of the first signal transfer protocol.   
     
     
         2 . The memory system of  claim 1 , wherein the control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be simultaneously performed by the other of the primary and secondary memories. 
     
     
         3 . The memory system of  claim 1 , wherein the first signal transfer protocol transfers a first quantity of bits substantially simultaneously, and the second signal transfer protocol transfers a second quantity of bits substantially simultaneously. 
     
     
         4 . The memory system of  claim 3 , wherein the first quantity of bits are transferred by the first signal transfer protocol between the primary memory and the controller, and the second quantity of bits are transferred by the second signal transfer protocol between the primary memory and the secondary memory in a same clock cycle. 
     
     
         5 . The memory system of  claim 2 , wherein the background operation is executed by one of the primary and secondary memory memories while a target output port of the one of the primary and secondary memories is not operating. 
     
     
         6 . The memory system of  claim 5 , wherein the background operation is one of a power-down operation, a precharge operation and a self-refresh operation. 
     
     
         7 . The memory system of  claim 2 , wherein when one of the foreground operation and background operation is a read operation, data from the secondary memory is received at the controller. 
     
     
         8 . The memory system of  claim 7 , wherein the data from the secondary memory is transferred through the primary memory to the controller. 
     
     
         9 . The memory system of  claim 1 , wherein the primary memory and the secondary memory are DRAM memories. 
     
     
         10 . The memory system of  claim 1 , wherein one of connection between the controller and the primary memory or between the primary memory and the secondary memory is a differential connection and the other connection is a single-ended connection. 
     
     
         11 . The memory system of  claim 1 , wherein the primary memory and the secondary memory are linked by a point-to-point link. 
     
     
         12 . The memory system of  claim 1 , wherein the first signal transfer protocol is n bit wide and the second signal transfer protocol is m bit wide, wherein n is greater than m, and m is a natural number.