Lateral insulated gate bipolar transistor

Abstract

A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.

1 . A lateral insulated gate bipolar transistor comprising a plurality of cells, each of the plurality of cells including:
 a semiconductor substrate including a drift layer of a first conductivity type;   a collector region of a second conductivity type disposed in a surface portion of the drift layer, the collector region having a longitudinal direction in a predetermined direction;   a channel layer of the second conductivity type disposed in the surface portion of the drift layer, the channel layer including a linear portion extending along either side of the collector region;   an emitter region of the first conductivity type disposed in a surface portion of the channel layer, an end of the emitter region located inside an end of the channel layer, the emitter region including a linear portion that has a longitudinal direction in the predetermined direction;   a gate insulating layer disposed on a surface of the channel layer located between the emitter region and the drift layer;   a gate electrode disposed on a surface of the gate insulating layer;   a collector electrode electrically coupled with the collector region;   an emitter electrode electrically coupled with the emitter region and the channel layer; and   a barrier layer of the first conductivity type disposed along either side of the collector region, the burrier layer located to a depth deeper than a bottom of the channel layer, the barrier layer having a first conductivity-type impurity concentration that is higher than a first conductivity-type impurity concentration of the drift layer, the barrier layer having a first end close to the collector region and a second end far from the collector region, the first end located between the channel layer and the collector region, the second end located on the bottom of the channel layer, wherein   the plurality of cells includes a first cell and a second cell adjacent to each other,   the emitter region and the channel layer in the first cell are arranged along with the emitter region and the channel layer in the second cell, and   the channel layer in the first cell is located at a predetermined distance from the channel layer in the second cell.   
     
     
         2 . The lateral insulated gate bipolar transistor according to  claim 1 , wherein
 the barrier layer includes a linear portion that has a longitudinal direction in the predetermined direction.   
     
     
         3 . The lateral insulated gate bipolar transistor according to  claim 2 , wherein
 the barrier layer further includes a corner portion that surrounds a longitudinal end of the collector region.   
     
     
         4 . The lateral insulated gate bipolar transistor according to  claim 3 , wherein
 the corner portion of the barrier layer has a first conductivity type impurity concentration that is lower than a first conductivity type impurity concentration of the linear portion of the barrier layer.   
     
     
         5 . The lateral insulated gate bipolar transistor according to  claim 1 , wherein
 the semiconductor substrate includes a support substrate, a buried oxide layer disposed on the support substrate, an active layer disposed on the buried oxide layer, a first conductivity type layer and a second conductivity type layer alternately arranged on a surface of the active layer being in contact with the buried oxide layer.   
     
     
         6 . The lateral insulated gate bipolar transistor according to  claim 1 , wherein
 the semiconductor substrate includes a support substrate, a buried oxide layer disposed on the support substrate, a first conductivity type layer disposed on the support substrate, and an active layer disposed on the first conductivity type layer.   
     
     
         7 . The lateral insulated gate bipolar transistor according to  claim 1 , wherein
 the collector region includes a high impurity concentration region and a low impurity concentration region,   the high impurity concentration region has an impurity concentration higher than an impurity concentration of the low impurity concentration region,   the collector electrode forms an ohmic junction with the high impurity concentration region, and   the collector electrode forms a schottky junction with the low impurity concentration region.   
     
     
         8 . The lateral insulated gate bipolar transistor according to  claim 7 , wherein
 the high impurity concentration region and the low impurity concentration region extend along the predetermined direction,   the plurality of cells includes a third cell and a fourth cell,   the high impurity concentration region in the third cell and the high impurity concentration region in the fourth cell have different widths.   
     
     
         9 . The lateral insulated gate bipolar transistor according to  claim 8 , wherein
 the semiconductor substrate includes a plurality of element regions each surrounded by an element isolating part, and   the third cell and the fourth cell are located in different element regions in the plurality element regions.   
     
     
         10 . The lateral insulated gate bipolar transistor according to  claim 7 , wherein
 the plurality of cells includes a third cell and a fourth cell,   the collector region in the third cell includes the high impurity concentration region and the low impurity concentration region, and   the collector region in the fourth cell includes only a region that forms an ohmic junction with the collector electrode.   
     
     
         11 . A lateral insulated gate bipolar transistor comprising a plurality of cells, each of the plurality of cells including:
 a semiconductor substrate including a drift layer of a first conductivity type;   a collector region of a second conductivity type disposed in a surface portion of the drift layer, the collector region having a longitudinal direction in a predetermined direction;   a channel layer of the second conductivity type disposed in the surface portion of the drift layer, the channel layer including a linear portion extending along either side of the collector region;   an emitter region of the first conductivity type disposed in a surface portion of the channel layer, an end of the emitter region located inside an end of the channel layer, the emitter region including a linear portion that has a longitudinal direction in the predetermined direction;   a gate insulating layer disposed on a surface of the channel layer located between the emitter region and the drift layer;   a gate electrode disposed on a surface of the gate insulating layer;   a collector electrode electrically coupled with the collector region;   an emitter electrode electrically coupled with the emitter region and the channel layer; and   a barrier layer of the first conductivity type disposed along either side of the collector region, the burrier layer located to a depth deeper than a bottom of the channel layer, the barrier layer having a first conductivity type impurity concentration that is higher than a first conductivity type impurity concentration of the drift layer, the barrier layer including a linear portion that has a longitudinal direction in the predetermined direction, the linear portion having a first conductivity type impurity peak concentration from 2×10 15  cm −3  to 1.5×10 16  cm −3 , wherein   the plurality of cells includes a first cell and a second cell adjacent to each other,   the emitter region and the channel layer in the first cell are arranged along with the emitter region and the channel layer located in the second cell,   the channel layer in the first cell is located at a predetermined distance from the channel layer in the second cell, and   the barrier layer covers the channel layer in the first cell and the channel layer in the second cell and is disposed also between the channel layer in the first cell and the channel layer in the second cell.   
     
     
         12 . The lateral insulated gate bipolar transistor according to  claim 11 , wherein
 the linear portion of the barrier layer includes a peak portion that has the first conductivity type impurity peak concentration, and   the peak portion is located at a depth of less than or equal to  0 . 5  μm from a surface of the barrier layer.   
     
     
         13 . The lateral insulated gate bipolar transistor according to  claim 11 , wherein
 the barrier layer further includes a corner portion that surrounds a longitudinal end of the collector region.   
     
     
         14 . The lateral insulated gate bipolar transistor according to  claim 12 , wherein
 the corner portion of the barrier layer has a first conductivity type impurity concentration that is lower than a first conductivity type impurity concentration of the linear portion of the barrier layer.   
     
     
         15 . A lateral insulated gate bipolar transistor comprising a plurality of cells, each of the plurality of cells including:
 a semiconductor substrate including a drift layer of a first conductivity type;   a collector region of a second conductivity type disposed in a surface portion of the drift layer, the collector region having a longitudinal direction in a predetermined direction;   a channel layer of the second conductivity type disposed in the surface portion of the drift layer, the channel layer including a linear portion extending along either side of the collector region;   an emitter region of the first conductivity type disposed in a surface portion of the channel layer, an end of the emitter region located inside an end of the channel layer, the emitter region including a linear portion that has a longitudinal direction in the predetermined direction;   a channel region provided on a surface of the channel layer between the emitter region and the drift layer;   a gate insulating layer disposed on a surface of the channel region;   a gate electrode disposed on a surface of the gate insulating layer;   a collector electrode electrically coupled with the collector region;   an emitter electrode electrically coupled with the emitter region and the channel layer; and   a trench provided from an end of the emitter region adjacent to the channel region, the trench having a corner portion at a bottom of the trench, the corner portion having a radius of curvature of greater than or equal to 0.5 μm, wherein   the plurality of cells includes a first cell and a second cell adjacent to each other,   the emitter region and the channel layer in the first cell are arranged along with the emitter region and the channel layer in the second cell,   the channel layer in the first cell is located at a predetermined distance from the channel layer in the second cell, and   the gate insulating layer and the gate electrode are disposed in the trench and the channel region is provided on the surface of the channel layer located on a sidewall of the trench.   
     
     
         16 . The lateral insulated gate bipolar transistor according to  claim 15 , wherein
 each of the plurality of cells further includes a barrier layer of the first conductivity type disposed along either side of the collector region, the burrier layer located to a depth deeper than a bottom of the channel layer, the barrier layer having a first conductivity type impurity concentration that is higher than a first conductivity type impurity concentration of the drift layer, the barrier layer including a linear portion that has a longitudinal direction in the predetermined direction.   
     
     
         17 . The lateral insulated gate bipolar transistor according to  claim 16 , wherein
 the barrier layer covers the channel layer in the first cell and the channel layer in the second cell and is disposed also between the channel layer in the first cell and the channel layer in the second cell.   
     
     
         18 . A lateral insulated gate bipolar transistor comprising a plurality of cells, each of the plurality of cells including:
 a semiconductor substrate including a drift layer of a first conductivity type;   a collector region of a second conductivity type disposed in a surface portion of the drift layer, the collector region having a longitudinal direction in a predetermined direction;   a channel layer of the second conductivity type disposed in the surface portion of the drift layer, the channel layer including a linear portion extending along either side of the collector region;   an emitter region of the first conductivity type disposed in a surface portion of the channel layer, an end of the emitter region located inside an end of the channel layer, the emitter region including a linear portion that has a longitudinal direction in the predetermined direction;   a gate insulating layer disposed on a surface of the channel layer located between the emitter region and the drift layer;   a gate electrode disposed on a surface of the gate insulating layer;   a collector electrode electrically coupled with the collector region;   an emitter electrode electrically coupled with the emitter region and the channel layer; and   a barrier layer of the first conductivity type disposed along either side of the collector region, the burrier layer located to a depth deeper than a bottom of the channel layer, the barrier layer having a first conductivity type impurity concentration that is higher than a first conductivity type impurity concentration of the drift layer, the barrier layer including a liner portion that has a longitudinal direction in the predetermined direction and a corner portion that surrounds a longitudinal end of the collector region, wherein   the plurality of cells includes a first cell and a second cell adjacent to each other,   the emitter region and the channel layer in the first cell are arranged along with the emitter region and the channel layer in the second cell,   the channel layer in the first cell is located at a predetermined distance from the channel layer in the second cell,   the linear portion of the barrier layer covers the channel layer in the first cell and the channel layer in the second cell and is disposed also between the channel layer in the first cell and the channel layer in the second cell, and   the corner portion of the barrier layer has a first end close to the collector region and a second end far from the collector region, the first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.