Scanning-line drive circuit

Abstract

A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.

1 . A scanning-line drive circuit driven by using at least three clock signals of different phases, and including a plurality of cascade-connected unit shift registers, wherein
 said plurality of unit shift registers include a specified unit shift register which activates an output signal when two of said three clock signals are both set at an activation level.   
     
     
         2 . The scanning-line drive circuit according to  claim 1 , wherein
 said specified unit shift register is the most preceding stage of the cascade connection.   
     
     
         3 . The scanning-line drive circuit according to  claim 2 , wherein
 an output signal of said specified unit shift register is supplied to a gate line connected to a pixel.   
     
     
         4 . The scanning-line drive circuit according to  claim 1 , wherein
 said specified unit shift register includes:
 an output terminal which outputs said output signal; 
 a clock terminal to which a first clock signal is supplied; 
 a first input terminal to which second clock signal is supplied; 
 a second input terminal to which a third clock signal is supplied; 
 a first transistor which supplies said first clock signal to said output terminal; and 
 a charge circuit connected to a first node to which a control electrode of said first transistor is connected, said charge circuit charging said first node when both of said second clock signal and said third clock signal are brought into the activation level. 
   
     
     
         5 . The scanning-line drive circuit according to  claim 4 , wherein
 said charge circuit includes a series circuit of a second transistor having a control electrode connected to said first input terminal and a third transistor having a control electrode connected to said second input terminal.   
     
     
         6 . The scanning-line drive circuit according to  claim 5 , wherein
 said series circuit is connected between a power source of a constant potential and said first node.   
     
     
         7 . The scanning-line drive circuit according to  claim 5 , wherein
 said series circuit is connected between said first node and said first or second input terminal.   
     
     
         8 . The scanning-line drive circuit according to  claim 4 , wherein
 said charge circuit is a fourth transistor having a control electrode connected to one of said first and second input terminals, and being connected between the other of said first and second input terminals and said first node.   
     
     
         9 . A scanning-line drive circuit driven by using at least three clock signals of different phases, and including a plurality of cascade-connected unit shift registers,
 said scanning-line drive circuit being operable to perform a forward-direction shift for shifting a signal from an immediately preceding stage toward a subsequent stage and a reverse-direction shift for shifting a signal from a subsequent stage toward a immediately preceding stage in said plurality of unit shift registers, wherein   said plurality of unit shift registers include:
 a first unit shift register which activates an output signal when two of said three clock signals are both set at an activation level at a time of the forward-direction shift; and 
 a second unit shift register which activates an output signal when two of said three clock signals are both set at the activation level at a time of the reverse-direction shift. 
   
     
     
         10 . The scanning-line drive circuit according to  claim 9 , wherein
 said first unit shift register is the most preceding stage of the cascade connection; and   said second unit shift register is the last stage of the cascade connection.   
     
     
         11 . The scanning-line drive circuit according to  claim 10 , wherein
 output signals of said first and second unit shift registers are supplied to gate lines connected to pixels, respectively.   
     
     
         12 . The scanning-line drive circuit according to  claim 9 , wherein
 said first unit shift register comprises:
 an output terminal which outputs said output signal; 
 a clock terminal to which a first clock signal is supplied; 
 a first input terminal to which a second clock signal is supplied; 
 a second input terminal to which a third clock signal is supplied; 
 a first voltage signal terminal to which supplied is a first voltage signal which is set at an activation level at a time of the forward-direction shift and at a deactivation level at a time of the reverse-direction shift; 
 a second voltage signal terminal to which supplied is a second voltage signal which is set at an activation level at a time of the reverse-direction shift and at a deactivation level at a time of the forward-direction shift; 
 a first transistor which supplies said first clock signal to said output terminal; 
 second and third transistors connected in series between said first voltage signal terminal and said first node; and 
 a fourth transistor having a control electrode to which an output signal of a next-stage unit shift register is inputted, said fourth transistor being connected between said first node and said second voltage signal terminal, 
   a control electrode of said second transistor is connected to said first input terminal,   a control electrode of said third transistor is connected to said second input terminal.   
     
     
         13 . The scanning-line drive circuit according to  claim 12 , wherein
 said first unit shift register is the most preceding stage of the cascade connection,   at a time of the reverse-direction shift, said second and third clock signals are both set at the activation level for a predetermined time period after an activation period of the output signal of said first unit shift register.   
     
     
         14 . The scanning-line drive circuit according to  claim 13 , wherein
 during said predetermined time period, said second voltage signal is set at the deactivation level.   
     
     
         15 . The scanning-line drive circuit according to  claim 9 , wherein
 said second unit shift register comprises:
 an output terminal which outputs said output signal; 
 a clock terminal to which a first clock signal is supplied; 
 a first input terminal to which a second clock signal is supplied; 
 a second input terminal to which a third clock signal is supplied; 
 a first voltage signal terminal to which supplied is a first voltage signal which is set at an activation level at a time of the forward-direction shift and at a deactivation level at a time of the reverse-direction shift; 
 a second voltage signal terminal to which supplied is a second voltage signal which is set at an activation level at a time of the reverse-direction shift and at a deactivation level at a time of the forward-direction shift; 
 a first transistor which supplies said first clock signal to said output terminal; 
 second and third transistors connected in series between said second voltage signal terminal and said first node; and 
 a fourth transistor having a control electrode to which an output signal of a unit shift register of an immediately preceding stage is inputted, said fourth transistor being connected between said first node and said first voltage signal terminal, 
   a control electrode of said second transistor is connected to said first input terminal,   a control electrode of said third transistor is connected to said second input terminal.   
     
     
         16 . The scanning-line drive circuit according to  claim 15 , wherein
 said second unit shift register is the last stage of the cascade connection,   at a time of the forward-direction shift, said second and third clock signals are both set at the activation level for a predetermined time period after an activation period of the output signal of said second unit shift register.   
     
     
         17 . The scanning-line drive circuit according to  claim 16 , wherein
 during said predetermined time period, said first voltage signal is set at the deactivation level.   
     
     
         18 . A scanning-line drive circuit driven by using at least two clock signals of different phases, and including a plurality of cascade-connected unit shift registers, wherein
 said scanning-line drive circuit is operable to perform a forward-direction shift for shifting a signal from an immediately preceding stage toward a subsequent stage and a reverse-direction shift for shifting a signal from a subsequent stage toward a immediately preceding stage in said plurality of unit shift registers,   said scanning-line drive circuit comprises:
 a first voltage signal terminal to which supplied is a first voltage signal which is set at an activation level at a time of the forward-direction shift and at a deactivation level at a time of the reverse-direction shift; and 
 a second voltage signal terminal to which supplied is a second voltage signal which is set at an activation level at a time of the reverse-direction shift and at a deactivation level at a time of the forward-direction shift, 
   said plurality of unit shift registers include:
 a first unit shift register which activates an output signal when said first and second voltage signals are both set at an activation level at a time of the forward-direction shift; and 
 a second unit shift register which activates an output signal when said first and second voltage signals are both set at the activation level at a time of the reverse-direction shift. 
   
     
     
         19 . The scanning-line drive circuit according to  claim 18 , wherein
 said first unit shift register is the most preceding stage of the cascade connection,   said second unit shift register is the last stage of the cascade connection.   
     
     
         20 . The scanning-line drive circuit according to  claim 19 , wherein
 output signals of said first and second unit shift registers are supplied to gate lines connected to pixels, respectively.   
     
     
         21 . The scanning-line drive circuit according to  claim 18 , wherein
 said first unit shift register comprises:
 an output terminal which outputs said output signal; 
 a clock terminal to which a first clock signal is supplied; 
 a first input terminal to which said first voltage signal is supplied; 
 a second input terminal to which said second voltage signal is supplied; 
 third input terminal to which a second clock signal is supplied; 
 a first transistor which supplies said first clock signal to said output terminal; 
 second and third transistors connected in series between said third input terminal and a first node to which a control electrode of said first transistor is connected; and 
 a fourth transistor having a control electrode to which an output signal of a next-stage unit shift register is inputted, said fourth transistor being connected between said first node and said second voltage signal terminal, 
   a control electrode of said second transistor is connected to said first input terminal,   a control electrode of said third transistor is connected to said second input terminal.   
     
     
         22 . The scanning-line drive circuit according to  claim 21 , wherein
 said first unit shift register is the most preceding stage of the cascade connection,   at a time of the reverse-direction shift, said first and second voltage signals are both set at the activation level and said second clock signal is set at the deactivation level, for a predetermined time period after an activation period of the output signal of said first unit shift register.   
     
     
         23 . The scanning-line drive circuit according to  claim 22 , wherein
 during said predetermined time period, said first clock signal is set at the deactivation level.   
     
     
         24 . The scanning-line drive circuit according to  claim 18 , wherein
 said second unit shift register comprises:
 an output terminal which outputs said output signal; 
 a clock terminal to which a first clock signal is supplied; 
 a first input terminal to which said first voltage signal is supplied; 
 a second input terminal to which said second voltage signal is supplied; 
 a third input terminal to which a second clock signal is supplied; 
 a first transistor which supplies said first clock signal to said output terminal; 
 second and third transistors connected in series between said third input terminal and a first node to which a control electrode of said first transistor is connected; and 
 a fourth transistor having a control electrode to which an output signal of a unit shift register of an immediately preceding stage is inputted, said fourth transistor being connected between said first node and said first voltage signal terminal, 
   a control electrode of said second transistor is connected to said first input terminal,   a control electrode of said third transistor is connected to said second input terminal.   
     
     
         25 . The scanning-line drive circuit according to  claim 24 , wherein
 said second unit shift register is the last stage of the cascade connection,   at a time of the forward-direction shift, said first and second voltage signals are both set at the activation level and said second clock signal is set at the deactivation level, for a predetermined time period after an activation period of the output signal of said second unit shift register.   
     
     
         26 . The scanning-line drive circuit according to  claim 25 , wherein
 during said predetermined time period, said first clock signal is set at the deactivation level.