Three dimensional semiconductor device

Abstract

Provided are a three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include a gate structure on a substrate with the gate structure including a plurality of gate electrodes. Conductive lines are disposed between the gate structure and the substrate. A horizontal semiconductor pattern is disposed between the gate structure and the conductive line. And a vertical semiconductor pattern penetrating the gate structure is connected to the horizontal semiconductor pattern.

1 . A three-dimensional semiconductor memory device, comprising:
 a gate structure on a substrate, the gate structure including a plurality of gate electrodes;   conductive lines between the gate structure and the substrate;   a horizontal semiconductor pattern between the gate structure and the conductive lines; and   a vertical semiconductor pattern penetrating the gate structure and connected to the horizontal semiconductor pattern.   
     
     
         2 . The three-dimensional semiconductor memory device of  claim 1 , wherein the conductive line is directly in contact with a bottom surface of the horizontal semiconductor pattern. 
     
     
         3 . The three-dimensional semiconductor memory device of  claim 1 , wherein the conductive line comprises at least a metal material, a conductive metal nitride, and/or a metal silicide. 
     
     
         4 . The three-dimensional semiconductor memory device of  claim 1 , wherein the conductive lines are substantially parallel to the gate electrodes. 
     
     
         5 . The three-dimensional semiconductor memory device of  claim 1 , wherein the horizontal semiconductor pattern has a same conductivity type as the vertical semiconductor pattern at a position adjacent to the vertical semiconductor pattern. 
     
     
         6 . The three-dimensional semiconductor memory device of  claim 1 , wherein the horizontal semiconductor pattern comprises a lower region adjacent to the conductive lines and an upper region adjacent to the gate electrodes,
 wherein the upper region has a same conductivity type as the vertical semiconductor pattern and the lower region has an opposite conductivity type to the upper region.   
     
     
         7 . The three-dimensional semiconductor memory device of  claim 1 , wherein the vertical semiconductor pattern has a hollow cylindrical shape and a thickness of the vertical semiconductor pattern is less than a thickness of the horizontal semiconductor pattern. 
     
     
         8 . The three-dimensional semiconductor memory device of  claim 1 , wherein a thickness of the horizontal semiconductor pattern and a thickness of an inversion layer formed in the horizontal semiconductor pattern by a predetermined voltage applied to a lowermost of the gate electrodes adjacent to the substrate are substantially equal. 
     
     
         9 . The three-dimensional semiconductor memory device of  claim 1 , wherein the vertical semiconductor pattern penetrates the horizontal semiconductor pattern to directly contact the conductive lines. 
     
     
         10 . The three-dimensional semiconductor memory device of  claim 1 , further comprising insulating layers between the gate electrodes and a support pattern disposed between the conductive lines under the horizontal semiconductor pattern, wherein the support pattern comprises an insulating material having an etching selectivity with respect to the insulating layers. 
     
     
         11 . The three-dimensional semiconductor memory device of  claim 1 , wherein the gate structure further comprises a data storage layer disposed between the gate electrodes and the vertical semiconductor pattern. 
     
     
         12 . The three-dimensional semiconductor memory device of  claim 11 , wherein the data storage layer extends on top and bottom surfaces of each of the gate electrodes. 
     
     
         13 . The three-dimensional semiconductor memory device of  claim 1 , further comprising an insulating spacer covering a sidewall of the gate structure, wherein the horizontal semiconductor pattern extends under the insulating spacer. 
     
     
         14 . The three-dimensional semiconductor memory device of  claim 1 , wherein the horizontal semiconductor pattern is a first horizontal semiconductor pattern and is separated from a second horizontal semiconductor pattern under another gate structure adjacent to the gate structure. 
     
     
         15 . The three-dimensional semiconductor memory device of  claim 1 , wherein the substrate comprises an insulating material, a semiconductor material, and/or a semiconductor covered with an insulating material. 
     
     
         16 - 20 . (canceled) 
     
     
         21 . A three-dimensional semiconductor memory device, comprising:
 first and second gate structures on a substrate, each of the first and second gate structures comprising a plurality of gate electrodes;   first and second horizontal semiconductor patterns disposed between the first and second gate structures and the substrate, respectively; and   a vertical semiconductor pattern disposed between the first and second gate structures on the substrate.   
     
     
         22 . The three-dimensional semiconductor memory device of  claim 21 , further comprising:
 first and second conductive lines disposed between the first and second horizontal semiconductor patterns and the substrate, respectively.   
     
     
         23 . The three-dimensional semiconductor memory device of  claim 22 , wherein the vertical semiconductor pattern directly contacts the first and second horizontal patterns without directly contacting the first and second conductive lines. 
     
     
         24 . The three-dimensional semiconductor memory device of  claim 22 , wherein the vertical semiconductor pattern directly contacts the first and second horizontal patterns and the first and second conductive lines. 
     
     
         25 . The three-dimensional semiconductor memory device of  claim 21 , further comprising a support pattern disposed between the vertical semiconductor pattern and the substrate.