Methods, devices, and systems for a high voltage tolerant buffer

Abstract

Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry that provide voltages to thin-gate dielectric transistors. One such buffer may include a primary pull-up pre-driver operably coupled to a primary pull-up transistor; a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor; a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. The pre-drivers may provide a sufficiently low voltage to a gate of a transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, wherein at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver is configured to provide a voltage greater than or equal to a ground voltage and less than or equal to a supply voltage.

1 . A buffer, comprising:
 a primary pull-up pre-driver operably coupled to a primary pull-up transistor;   a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor;   a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and   a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor;   wherein the primary pull-up pre-driver, the secondary pull-up pre-driver, the primary pull-down pre-driver, and the secondary pull-down pre-driver are each configured to provide a sufficiently low voltage to a gate of a transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, and wherein at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver is configured to provide a voltage greater than or equal to a ground voltage (VSSQ) and less than or equal to a supply voltage (VCCQ).   
     
     
         2 . The buffer of  claim 1 , wherein the primary pull-up pre-driver comprises:
 an inverter operably coupled between an input signal and a first transistor of the primary pull-up pre-driver; and   a buffer operably coupled between the input signal and a second transistor of the primary pull-up pre-driver.   
     
     
         3 . The buffer of  claim 2 , wherein the secondary pull-down pre-driver comprises:
 an inverter operably coupled between an input signal and a first transistor of the primary pull-down pre-driver; and   a buffer operably coupled between the input signal and a second transistor of the primary pull-down pre-driver.   
     
     
         4 . The buffer of  claim 1 , wherein the secondary pull-up pre-driver comprises:
 an inverter having an input operably coupled to an input signal and an output operably coupled to a gate of a first transistor and a gate of a second transistor; and   an output operably coupled between a source of the second transistor and a source of the first transistor.   
     
     
         5 . The buffer of  claim 4 , wherein a drain of the first transistor is operably coupled to a supply voltage, a drain of the second transistor is operably coupled to a ground voltage, and a source of the first transistor is operably coupled to a source of the second transistor. 
     
     
         6 . The buffer of  claim 1 , wherein the secondary pull-down pre-driver comprises:
 an inverter having an input operably coupled to an input signal and an output operably coupled to a gate of a first transistor and a gate of a second transistor; and   an output operably coupled between a source of the second transistor and a source of the first transistor.   
     
     
         7 . The buffer of  claim 6 , wherein a drain of the first transistor is operably coupled to a supply voltage, a drain of the second transistor is operably coupled to a ground voltage, and a source of the first transistor is operably coupled to a source of the second transistor. 
     
     
         8 . The buffer of  claim 1 , wherein at least one of the primary pull-up pre-driver and the primary pull-down pre-driver further comprises an output operably coupled between a drain of a first transistor and a source of a second transistor. 
     
     
         9 . The buffer of  claim 1 , further comprising one or more clamping devices operably coupled to a gate of a transistor that is operably coupled to an output of at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, the primary pull-down pre-driver, and the secondary pull-down pre-driver. 
     
     
         10 . The buffer of  claim 9 , wherein at least one of the one or more clamping devices is configured to be selectively enabled and disabled. 
     
     
         11 . The buffer of  claim 1 , further comprising one or more clamping devices configured to maintain a voltage of an output node of at least one of the primary pull-up pre-driver and the secondary pull-up pre-driver above a predefined threshold voltage. 
     
     
         12 . The buffer of  claim 1 , further comprising one or more clamping devices configured to maintain a voltage of an output node of at least one of the primary pull-down pre-driver and the secondary pull-down pre-driver below a predefined threshold voltage 
     
     
         13 . A buffer, comprising:
 a primary pull-up pre-driver operably coupled to a primary pull-up transistor;   a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor;   a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and   a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor;   wherein the primary pull-up pre-driver, the secondary pull-up pre-driver, the primary pull-down pre-driver, and the secondary pull-down pre-driver are each configured to provide a sufficiently low voltage to a gate of the transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, and wherein at least one of the secondary pull-up pre-driver and the secondary pull-down pre-driver comprises:
 an inverter having an input operably coupled to an input signal and an output operably coupled to a gate of a first transistor and a gate of a second transistor, wherein a drain of the first transistor is operably coupled to a supply voltage, a drain of the second transistor is operably coupled to a ground voltage, and a source of the first transistor is operably coupled to a source of the second transistor; and 
 an output operably coupled between the source of the second transistor and the source of the first transistor. 
   
     
     
         14 . A semiconductor device, comprising:
 at least one buffer comprising:
 a primary pull-up pre-driver configured to provide a sufficiently low first voltage to a primary pull-up transistor so as to sustain a gate dielectric integrity of the primary pull-up transistor; 
 a secondary pull-up pre-driver configured to provide a sufficiently low second voltage to a secondary pull-up transistor so as to sustain a gate dielectric integrity of the secondary pull-up transistor; 
 a primary pull-down pre-driver configured to provide a sufficiently low third voltage to a primary pull-down transistor so as to sustain a gate dielectric integrity of the primary pull-down transistor; and 
 a secondary pull-down pre-driver configured to provide a sufficiently low fourth voltage to a secondary pull-down transistor so as to sustain a gate dielectric integrity of the secondary pull-down transistor, 
 wherein at least one of the sufficiently low first voltage, the sufficiently low second voltage, the sufficiently low third voltage, or the sufficiently low fourth voltage is greater than or equal to a ground voltage and less than or equal to a supply voltage. 
   
     
     
         15 . A buffer, comprising:
 a primary pull-up pre-driver adapted to drive a primary pull-up transistor;   a secondary pull-up pre-driver adapted to drive a secondary pull-up transistor;   a primary pull-down pre-driver adapted to drive a primary pull-down transistor;   a secondary pull-down pre-driver adapted to drive a secondary pull-down transistor; and   at least one clamping device, wherein at least one of a gate of the primary pull-up transistor, the secondary pull-up transistor, the primary pull-down transistor, or the secondary pull-down transistor is coupled to a clamping device of the at least one clamping device;   wherein the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver are each adapted to drive the transistor operably coupled thereto with a sufficiently low voltage so as to sustain a gate dielectric integrity of the transistor.   
     
     
         16 . A method of operating a buffer, the method comprising:
 providing a sufficiently low first voltage from a primary pull-up pre-driver to a gate of a primary pull-up transistor so as to sustain a gate dielectric integrity of the primary pull-up transistor;   providing a sufficiently low second voltage from a secondary pull-up pre-driver to a gate of a secondary pull-up transistor so as to sustain a gate dielectric integrity of the secondary pull-up transistor;   providing a sufficiently low third voltage from a primary pull-down pre-driver to a gate of a primary pull-down transistor so as to sustain a gate dielectric integrity of the primary pull-down transistor;   providing a sufficiently low fourth voltage from a secondary pull-down pre-driver to a gate of a secondary pull-down transistor so as to sustain a gate dielectric integrity of the secondary pull-down transistor; and   holding a bulk node of the secondary pull-down transistor to the lower of a source voltage of the secondary pull-down transistor and a drain voltage of the secondary pull-down transistor.   
     
     
         17 . The method of  claim 12 , further comprising holding a bulk node of the secondary pull-up transistor to the lower of a source voltage and a drain voltage of the secondary pull-up transistor. 
     
     
         18 . The method of  claim 12 , further comprising clamping a voltage of at least one of a gate of the primary pull-up transistor, a gate of the secondary pull-up transistor, a gate of the primary pull-down transistor, and a gate of the secondary pull-down transistor. 
     
     
         19 . The method of  claim 12 , further comprising clamping a voltage of each gate of the primary pull-up transistor, a gate of the secondary pull-up transistor, a gate of the primary pull-down transistor, and a gate of the secondary pull-down transistor. 
     
     
         20 . The method of  claim 12 , wherein at least one of providing a sufficiently low first voltage, providing a sufficiently low second voltage, providing a sufficiently low third voltage, and providing a sufficiently low fourth voltage comprises providing a voltage from the respective pre-driver to the respective gate such that each of a gate-to-source, a gate-to-drain, and a source-to-drain voltage drop is less than 1.35 volts.