Functional DMA

Abstract

In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

1 . A direct memory access (DMA) controller comprising:
 a transmit control circuit configured to read first DMA data from an address space in a host for a first DMA transfer, wherein the first DMA transfer includes at least a first operation to be performed on the first DMA data to produce a result, and wherein the first DMA data comprises packet data that is to be transmitted on a packet interface;   a circuit coupled to receive the first DMA data, wherein the circuit is configured to perform the first operation on the first DMA data to produce the result; and   wherein the DMA controller is configured to transmit the result to an interface circuit that is configured to transmit the result on the packet interface.   
     
     
         2 . The DMA controller as recited in  claim 1  wherein the first operation is encryption of the packet data, wherein the result is an encrypted packet to be transmitted on the packet interface. 
     
     
         3 . The DMA controller as recited in  claim 1  wherein the first operation is checksum generation, and wherein the result is a checksum to be inserted in a packet header of a packet that includes the packet data. 
     
     
         4 . The DMA controller as recited in  claim 1  wherein the first operation is a cyclical redundancy check (CRC) data generation, and wherein the result is CRC data to be appended to the packet data. 
     
     
         5 . A system comprising:
 a memory system;   an interface circuit configured to transmit data on an interface; and   a direct memory access (DMA) controller coupled to memory system and to the interface circuit, wherein the DMA controller is configured to perform a DMA transfer from the memory system, and wherein the DMA controller is configured to perform at least a first operation on first DMA data read from the memory system for the DMA transfer, the first operation producing a result, and wherein the DMA controller is configured to transmit the result to the interface circuit for transmission on the interface.   
     
     
         6 . The system as recited in  claim 5  wherein the first operation is a transformation of the first DMA data to the result, and wherein the DMA controller is configured to transmit the result instead of the first DMA data to the interface circuit. 
     
     
         7 . The system as recited in  claim 6  wherein the transformation comprises encryption. 
     
     
         8 . The system as recited in  claim 7  wherein the transformation further comprises hashing. 
     
     
         9 . The system as recited in  claim 8  wherein the DMA controller comprises a hash circuit and an encryption circuit, wherein an output of the hash circuit is coupled to an input of the encryption circuit, and wherein an output of the encryption circuit is coupled to an input of the hand circuit, whereby the DMA controller supports encryption and hashing in either order. 
     
     
         10 . The system as recited in  claim 5  wherein the interface circuit is configured to communicate on the interface according to a network interface protocol. 
     
     
         11 . The system as recited in  claim 10  wherein the interface circuit is a media access control (MAC) unit for the network interface protocol. 
     
     
         12 . The system as recited in  claim 5  wherein the DMA controller is configured to transmit the result to the interface circuit in addition to the first DMA data. 
     
     
         13 . The system as recited in  claim 12  wherein the first operation is checksum generation, and wherein the result is a checksum. 
     
     
         14 . The system as recited in  claim 13  wherein the first DMA data is packet data, and wherein the checksum is inserted in a packet header of a packet that includes the packet data. 
     
     
         15 . The system as recited in  claim 12  wherein the first operation is a cyclical redundancy check (CRC) data generation, and wherein the result is CRC data to be appended to the first DMA data. 
     
     
         16 . A method comprising:
 performing a direct memory access (DMA) transfer from memory to a packet interface circuit;   during the DMA transfer, performing at least a first operation on packet data read from the memory to produce a result; and   transmitting the result to the packet interface circuit.   
     
     
         17 . The method as recited in  claim 16  wherein the first operation transforms the packet data to transformed packet data, wherein the result is the transformed packet data, and wherein the method further comprises transmitting the transformed packet data on a packet interface to which the packet interface circuit is coupled. 
     
     
         18 . The method as recited in  claim 16  further comprising:
 transmitting the packet data to the packet interface circuit; and 
 the packet interface circuit transmitting the packet data and the result on a packet interface to which the packet interface circuit is coupled. 
 
     
     
         19 . The method as recited in  claim 18  wherein the result is a checksum, and wherein the packet interface circuit transmitting the packet data and the result on a packet interface comprises the packet interface inserting the checksum in a packet header of a packet that includes the packet data. 
     
     
         20 . The method as recited in  claim 18  wherein the result is cyclical redundancy check (CRC) data, and wherein the packet interface circuit transmitting the packet data and the result on a packet interface comprises the packet interface appending the CRC data to the packet data.