Thin film transistor backplane

Abstract

A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.

1 - 12 . (canceled) 
     
     
         13 . A system comprising:
 a self-aligned structure including a plurality of gate lines and a plurality of rows of thin-film transistors that are respectively gated by the gate lines;   a passivation layer overlying the self-aligned thin-film structure; and   conductive traces that are on the passivation layer and subject to alignment variations relative to the self-aligned structure, wherein the conductive traces include a plurality of data lines that cross over the gate lines, each of the data lines being coupled to a column of the thin-film transistors.   
     
     
         14 . The system of  claim 13 , further comprising an array of pixels, wherein the conductive traces further comprise pixel electrodes that are coupled to respective pixels. 
     
     
         15 . The system of  claim 14 , wherein the pixels comprise LCD pixels. 
     
     
         16 . The system of  claim 14 , wherein the pixels comprise electrophoretic pixels. 
     
     
         17 . The system of  claim 14 , wherein each of the data lines includes a continuous portion and a plurality of necks, the necks being between the continuous portion of the data line and the thin-film transistors in the column coupled to the data line. 
     
     
         18 . The system of  claim 17 , wherein one of the necks is cut so that a corresponding one of the thin film transistors is isolated from the continuous portion of the data line. 
     
     
         19 . The system of  claim 13 , wherein the self-aligned structure further comprises:
 a plurality of drive transistors; and   a plurality of capacitors; the capacitors having plates that extend to form respective gates of the drive transistors.   
     
     
         20 . The system of  claim 19 , further comprising an array of light emitting diodes overlying the passivation layer, wherein each of the light emitting diodes is connected in series with a corresponding one of the drive transistors. 
     
     
         21 . The system of  claim 13 , wherein the system forms a backplane of a flat panel display.