Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained

Abstract

Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.

1 . A semiconductor device comprising:
 a first main electrode extension and a second main electrode extension formed in a semiconductor substrate;   an insulating layer formed on the semiconductor substrate; and   a control electrode formed over the insulating layer;   wherein the insulating layer has an overlap with each main electrode extension and the insulating layer has a first unfilled recess near the first main electrode extension having a depth of less than a width of an overlap between the control electrode and the first main electrode extension and/or a second unfilled recess near the second main electrode extension having a depth of less than a width of an overlap between the control electrode and the second main electrode extension, wherein the first and/or second recesses comprise a sloped sidewall, and wherein the first and/or second recesses remain unfilled.   
     
     
         2 . The semiconductor device of  claim 1 , wherein each recess has a depth between about 0.5 and 5 nanometers. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the control electrode has a length of less than about 100 nm. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the control electrode has a length of less than about 50 nm. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the overlap between the insulating layer and each main electrode extension is between about 10 and 20% of a length of the control electrode. 
     
     
         6 . The semiconductor device of  claim 1 , wherein an overlap between the control electrode and the first and second main electrode extensions is between about 10 and 20% of a length of the control electrode. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the insulating layer comprises silicon oxide. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the control electrode comprises silicon. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the control electrode comprises a polycrystalline material. 
     
     
         10 . A semiconductor device comprising:
 a first main electrode extension and a second main electrode extension formed in a semiconductor substrate;   an insulating layer formed on the semiconductor substrate;   a control electrode formed over the insulating layer; and   a spacer for deep source and drain implants;   wherein the insulating layer has an overlap with each main electrode extension and the insulating layer has a first unfilled recess near the first main electrode extension having a depth of less than a width of an overlap between the control electrode and the first main electrode extension and/or a second unfilled recess near the second main electrode extension having a depth of less than a width of an overlap between the control electrode and the second main electrode extension, wherein the first and/or second recesses comprise a sloped sidewall, and wherein the spacer does not fill the first and/or second recesses.   
     
     
         11 . A semiconductor device comprising:
 a first main electrode extension and a second main electrode extension formed in a semiconductor substrate;   an insulating layer formed on the semiconductor substrate; and   a control electrode formed over the insulating layer;   wherein the insulating layer has an overlap with each main electrode extension and the insulating layer has a first recess near the first main electrode extension having a depth of less than a width of an overlap between the control electrode and the first main electrode extension and/or a second recess near the second main electrode extension having a depth of less than a width of an overlap between the control electrode and the second main electrode extension, and wherein the first and/or second recesses comprise a sloped sidewall.   
     
     
         12 . The device of  claim 11 , wherein the sloped sidewall tapers inward in the direction of the semiconductor substrate.