Digitally controlled oscillators

Abstract

Oscillator circuitry is provided that is based on a ring of inverters. The ring of inverters may be single-ended or differential inverters. Digitally controlled adjustable load capacitors may be provided at inverter outputs to tune the oscillator circuitry. Each digitally controlled adjustable load capacitor may be formed from multiple varactors connected in parallel. Each varactor may have a control input that receives a digital control signal. The digitally controlled adjustable load capacitors in a given oscillator may be adjusted in unison to produce the same capacitance value for each capacitor or may be adjusted individually so that they produce different capacitance values. The inverters may include common-mode-gain reduction features such as series-connected current sources, series-connected resistors, and cross-coupled negative feedback transistors.

1 . A method of adjusting a ring of inverters coupled to at least first and second adjustable capacitors, the method comprising:
 applying a first digital control word to the first adjustable capacitor operable to direct the first adjustable capacitor to produce a first capacitance value;   applying a second digital control word to the second adjustable capacitor operable to direct the second adjustable capacitor to produce a second capacitance value that is different from the first capacitance value; and   ensuring that the first digital control word and the second digital control word contain respective numbers of logic high signals that differ by no more than a given number to avoid excessive capacitance mismatches between the first and second capacitance values.   
     
     
         2 . The method defined in  claim 1  wherein the given number is one. 
     
     
         3 . The method defined in  claim 1  wherein the first adjustable capacitor comprises a first plurality of parallel-coupled capacitors and wherein applying the first digital control word comprises:
 applying logic high signals to at least one of the capacitors in the first plurality of parallel-coupled capacitors; and 
 applying logic low signals to at least one of the capacitors in the first plurality of parallel-coupled capacitors. 
 
     
     
         4 . The method defined in  claim 3  wherein the second adjustable capacitor comprises a second plurality of parallel-coupled capacitors and wherein applying the second digital control word comprises:
 applying logic high signals to at least one of the capacitors in the second plurality of parallel-coupled capacitors; and 
 applying logic low signals to at least one of the capacitors in the second plurality of parallel-coupled capacitors. 
 
     
     
         5 . The method defined in  claim 1  wherein the ring of inverters is coupled to at least a third adjustable capacitor, the method further comprising:
 applying a third digital control word to the third adjustable capacitor operable to direct the third adjustable capacitor to produce a third capacitance value that is the same as the first capacitance value. 
 
     
     
         6 . The method defined in  claim 5  wherein the ring of inverters is coupled to at least a fourth adjustable capacitor, the method further comprising:
 applying a fourth digital control word to the fourth adjustable capacitor operable to direct the fourth adjustable capacitor to produce a fourth capacitance value that is the same as the second capacitance value. 
 
     
     
         7 . A method of adjusting a ring of inverters coupled to at least first and second adjustable capacitors, the method comprising:
 applying a first digital control word to the first adjustable capacitor operable to direct the first adjustable capacitor to produce a first capacitance value;   applying a second digital control word to the second adjustable capacitor operable to direct the second adjustable capacitor to produce a second capacitance value that is different from the first capacitance value; and   avoiding excessive capacitance mismatches between the first and second capacitance values.   
     
     
         8 . The method defined in  claim 7  wherein avoiding excessive capacitance mismatches between the first and second capacitance values comprises:
 ensuring that the first digital control word and the second digital control word contain respective numbers of logic low signals that differ by no more than a given number to avoid excessive capacitance mismatches between the first and second capacitance values. 
 
     
     
         9 . The method defined in  claim 8  wherein the given number is one. 
     
     
         10 . An integrated circuit comprising:
 at least first and second adjustable capacitors;   a ring of inverters coupled to the adjustable capacitors; and   circuitry operable to apply a first digital control word to the first adjustable capacitor operable to direct the first adjustable capacitor to produce a first capacitance value, wherein the circuitry is operable to apply a second digital control word to the second adjustable capacitor operable to direct the second adjustable capacitor to produce a second capacitance value that is different from the first capacitance value and wherein the circuitry is operable to avoid excessive capacitance mismatches between the first and second capacitance values.   
     
     
         11 . The integrated circuit defined in  claim 10  wherein the circuitry is operable to ensure that the first digital control word and the second digital control word contain respective numbers of logic low signals that differ by no more than a given number. 
     
     
         12 . The integrated circuit defined in  claim 10  wherein the circuitry is operable to ensure that the first digital control word and the second digital control word contain respective numbers of logic low signals that differ by no more than one. 
     
     
         13 . The integrated circuit defined in  claim 10  wherein the circuitry is operable to ensure that the first digital control word and the second digital control word contain respective numbers of logic high signals that differ by no more than a given number. 
     
     
         14 . The integrated circuit defined in  claim 10  wherein the circuitry is operable to ensure that the first digital control word and the second digital control word contain respective numbers of logic high signals that differ by no more than one. 
     
     
         15 . The integrated circuit defined in  claim 10  further comprising:
 a third adjustable capacitor coupled to the ring of inverters, wherein the circuitry is operable to apply a third digital control word to the third adjustable capacitor operable to direct the third adjustable capacitor to produce a third capacitance value that is the same as the first capacitance value. 
 
     
     
         16 . The integrated circuit defined in  claim 15  further comprising:
 a fourth adjustable capacitor coupled to the ring of inverters, wherein the circuitry is operable to apply a fourth digital control word to the fourth adjustable capacitor operable to direct the fourth adjustable capacitor to produce a fourth capacitance value that is the same as the second capacitance value.