Semiconductor memory devices including asymmetric word line pads

Abstract

Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed.

1 . A semiconductor memory device, comprising:
 a semiconductor substrate;   a first stack on the semiconductor substrate, the first stack including a plurality of first word lines with a plurality of first word line pads, a structure of at least one side of the plurality of first word line pads being stair-type; and   a second stack on the first stack, the second stack including a plurality of second word lines with a plurality of second word line pads, a structure of at least one side of the plurality of second word line pads being stair-type, the second stack shifted on the first stack such that the plurality of first word line pads on at least one side of the first stack are exposed.   
     
     
         2 . The device of  claim 1 , further comprising:
 a plurality of first pad contacts in contact with the exposed plurality of first word line pads and connecting the plurality of first word lines to a driving circuit; and   a plurality of second pad contacts in contact with the plurality of second word line pads and connecting the plurality of second word lines to the driving circuit.   
     
     
         3 . The device of  claim 2 , wherein the at least one side of the plurality of first word line pads is at least first and second sides, the first side on an opposite side of the first stack from the second side, and
 the at least one side of the plurality of second word line pads is at least third and fourth sides, the third side on an opposite side of the second stack from the fourth side.   
     
     
         4 . The device of  claim 3 , wherein the plurality of first pad contacts are in contact with the plurality of first word line pads on the first side,
 the plurality of second pad contacts are in contact with the plurality of second word line pads on the third side, and   the third side is on the first side.   
     
     
         5 . The device of  claim 4 , wherein the plurality of first pad contacts and the plurality of second pad contacts are alternately arranged in a direction orthogonal to the first and third sides. 
     
     
         6 . The device of  claim 3 , wherein the plurality of first pad contacts are in contact with the plurality of first word line pads on the first side,
 the plurality of second pad contacts are in contact with the plurality of second word line pads on the fourth side, and   the fourth side is on an opposite side of the first and second stacks from the first side.   
     
     
         7 . The device of  claim 2 , further comprising:
 at least one third stack between the first and second stacks, the at least one third stack including a plurality of third word lines with a plurality of third word line pads, a structure of at least one side of the plurality of third word line pads being stair-type.   
     
     
         8 . The device of  claim 7 , wherein the third stack is shifted on the first stack such that the plurality of first word line pads on at least one side of the first stack are exposed, and
 the second stack is shifted on the third stack such that the plurality of third word line pads on at least one side of the third stack are exposed.   
     
     
         9 . The device of  claim 1 , wherein a size of the first stack is greater than or equal to a size of the second stack. 
     
     
         10 . The device of  claim 1 , further comprising:
 a plurality of channels penetrating the first and the second stacks; and   a plurality of bit lines electrically connected to the plurality of channels,   wherein the plurality of channels are at least one of arranged linearly in one direction or arranged to zigzag in the one direction.   
     
     
         11 . The device of  claim 1 , wherein:
 the first stack further includes at least one first selection line, the plurality of first word lines between the at least one first selection line and the second stack; and   the second stack further includes at least one second selection line, the plurality of second word lines between the at least one second selection line and the first stack,   wherein the at least one first selection line includes a first selection line pad, a structure including the first selection line pad and the plurality of first word line pads being stair type, and   the at least one second selection line includes a second selection line pad, a structure including the second selection line pad and the plurality of second word line pads being stair-type.   
     
     
         12 . The device of  claim 11 , wherein:
 the first stack further includes a first dummy word line between the plurality of first word lines and the at least one first selection line; and   the second stack further includes a second dummy word line between the plurality of second word lines and the at least one second selection line.   
     
     
         13 . The device of  claim 1 , further comprising:
 a third stack spaced apart from the first stack by a first distance in a direction orthogonal to a direction intersecting the first and second stacks, a structure of the third stack the same as a structure of the first stack; and   a fourth stack on the third stack and spaced apart from the second stack by the first distance in the orthogonal direction, a structure of the fourth stack the same as a structure of the second stack, the fourth stack shifted on the third stack such that a part of a side of the third stack is exposed.   
     
     
         14 . A semiconductor memory device, comprising:
 a first stack including a plurality of first word line pads, a structure of at least one side of the plurality of first word line pads being stair-type; and   a second stack stacked on the first stack, the second stack including a plurality of second word line pads, a structure of at least one side of the plurality of second word line pads being stair-type, the plurality of second word line pads covering at least a part of the plurality of first word line pads and exposing sides of the plurality of first word line pads.   
     
     
         15 . The device of  claim 14 , further comprising:
 a plurality of first pad contacts contacting the plurality of first word line pads; and   a plurality of second pad contacts contacting the plurality of second word line pads,   wherein the plurality of first pad contacts do not overlap the plurality of second pad contacts.   
     
     
         16 . The device of  claim 14 , further comprising:
 at least one third stack between the first and second stacks, the at least one third stack including a plurality of third word line pads, a structure of at least one side of the plurality of third word line pads being stair-type,   wherein the plurality of third word line pads cover at least part of the plurality of first word line pads and expose the sides of the plurality of first word line pads, and   the plurality of second word line pads cover at least a part of the plurality of third word line pads and expose sides of the plurality of third word line pads.   
     
     
         17 . A semiconductor device, comprising:
 a substrate layer;   a multilayer structure on the substrate layer, the multilayer structure including
 a first stack including at least three first layers on the substrate layer, sidewalls of the first layers offset from each other on at least one first side of the multilayer structure such that at least a portion of each of the first layers is exposed in the first stack, and 
 a second stack including at least three second layers on the first stack, sidewalls of the second layers offset from each other on at least one second side of the multi-layer structure such that at least a portion of each of the second layers is exposed in the second stack, a side of the first stack offset from a side of the second stack on at least one third side of the multilayer structure such that at least a portion of the first stack is exposed in the multilayer structure, the at least one third side orthogonal to the at least one first and second sides. 
   
     
     
         18 . The semiconductor device of  claim 17 , wherein the at least one first and second sides are a same side of the multilayer structure. 
     
     
         19 . The semiconductor device of  claim 17 , wherein the at least one first side includes at least two sides of the multilayer structure, sidewalls of the first layers offset from each other on each of the at least two sides, and
 the at least one second side includes the at least two sides of the multilayer structure, and sidewalls of the second layers are offset from each other on each of the at least two sides.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising:
 a third stack including at least three third layers on the second stack, sidewalls of the third layers offset from each other on each of the at least two sides of the multi-layer structure such that at least a portion of each of the third layers is exposed in the third stack, a side of the third stack offset from the side of the second stack on the at least one third side of the multilayer structure such that at least a portion of the second stack is exposed in the multilayer structure.