US2011316157A1PendingUtilityA1

Semiconductor device and a method for manufacturing the same

Assignee: SAKAMOTO TATSUYAPriority: May 21, 2008Filed: Sep 13, 2011Published: Dec 29, 2011
Est. expiryMay 21, 2028(~1.8 yrs left)· nominal 20-yr term from priority
H10W 72/9415H10W 72/942H10W 72/934H10W 72/923H10W 72/251H10W 72/242H10W 72/221H10W 72/29H10W 72/019H10W 70/05H10W 20/49H10W 72/20H10W 42/121H10W 74/129
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Claims

Abstract

A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a semiconductor chip;   a sealing resin layer formed on the semiconductor chip;   a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface; and   an external connecting terminal formed on a top surface of the post electrode and protruding from a surface of the sealing resin layer,   wherein the post electrode comprises a base portion made of a first metal material, and a top edge portion made of a second metal material different from the first metal material and formed on the base portion, and   wherein a diameter of the base portion and a diameter of the top edge portion at the contact surface between the base portion and the top edge portion are the same size, and   wherein the base portion is formed into a columnar shape, and the top edge portion is formed into a hemispheric shape.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the base portion is buried in the through-hole, and an interface between the base portion and the top edge portion is positioned at the side of the semiconductor chip with respect to a surface of the sealing resin layer. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein a melting point of the second metal material is lower than a melting point of the first metal material. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the first metal material comprises copper and the second metal material comprises tin. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein a center and a top portion of the post electrode protrudes from a surface of the sealing resin layer. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein a maximum diameter of the external connecting terminal is smaller than a length which is 1.3 times the diameter of the post electrode. 
     
     
         7 . A semiconductor device, comprising:
 a semiconductor chip;   an insulating layer formed on the semiconductor chip; and   a pad opening for exposing an inner wiring formed on the semiconductor chip; and   a post electrode formed on the pad opening and having a column shaped base portion and a hemispheric shaped top edge portion,   wherein the base portion is made of a first metal material and the top edge portion is made of a second metal material different from the first metal material, and   wherein a diameter of the base portion and a diameter of the top edge portion at the contact surface between the base portion and the top edge portion are the same size.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein a melting point of the second metal material is lower than a melting point of the first metal material. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein a length of a chord corresponding to an arc formed by the hemispheric shaped top edge portion is not bigger than 320 μm. 
     
     
         10 . The semiconductor device according to  claim 7 , wherein the semiconductor device includes a semiconductor device applied WLCSP (Wafer Level Chip Size Package) technology. 
     
     
         11 . The semiconductor device according to  claim 7 , further comprising a passivation film which protects a surface of the semiconductor chip formed on the semiconductor chip. 
     
     
         12 . The semiconductor device according to  claim 11 , further comprising a rewiring formed on the passivation film. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein the passivation film is made of an oxide silicon or a nitride silicon. 
     
     
         14 . The semiconductor device according to  claim 12 , wherein a pad opening is formed in the passivation film to expose a part of an internal wiring of the semiconductor chip. 
     
     
         15 . The semiconductor device according to  claim 12 , wherein the rewiring is made of copper.

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