US2011320699A1PendingUtilityA1

System Refresh in Cache Memory

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Assignee: BLAKE MICHAELPriority: Jun 24, 2010Filed: Jun 24, 2010Published: Dec 29, 2011
Est. expiryJun 24, 2030(~3.9 yrs left)· nominal 20-yr term from priority
G06F 12/0897G06F 13/1605G11C 11/40603G06F 13/1636G11C 11/406G11C 11/40618G11C 11/40607G06F 13/14G06F 13/16
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Claims

Abstract

System refresh in a cache memory includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory, activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory, receiving a refresh grant in response to activating the refresh request, and transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.

Claims

exact text as granted — not AI-modified
1 . A computer program product for system refresh in a cache memory, comprising a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
 generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory;   activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory;   receiving a refresh grant in response to activating the refresh request; and   transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.   
     
     
         2 . The computer program product of  claim 1 , wherein the RTIM pulse is generated at the beginning of a refresh time interval. 
     
     
         3 . The computer program product of  claim 2 , wherein the refresh time period pulse denotes the beginning of an interval during which all embedded dynamic random access memory (EDRAM) macros of the single cache memory bank must be refreshed to retain their contents. 
     
     
         4 . The computer program product of  claim 1 , wherein the central refresh controller generates a new RTIM pulse every N clock cycles, where N is a number of clock cycles within a predetermined refresh period. 
     
     
         5 . The computer program product of  claim 4 , wherein the predetermined refresh period is determined based upon at least one of system operating voltage and system temperature of the cache memory. 
     
     
         6 . The computer program product of  claim 1 , wherein the refresh grant is received from a bank availability model in communication with the central refresh controller activating the refresh request, and the bank availability model is configured to perform a method, comprising:
 receiving the refresh request;   suppressing availability of the single cache memory bank in response to the received refresh request;   determining if there is an available time slot for granting the refresh request; and   issuing the refresh grant in response to the determining.   
     
     
         7 . The computer program product of  claim 1 , wherein a plurality of different RTIM pulses are generated for a plurality of different bank controllers, each bank controller being local to, and associated with, only one cache memory bank of the cache memory, and each cache memory bank of the cache memory being associated with only one bank controller. 
     
     
         8 . The computer program product of  claim 7 , wherein the plurality of different RTIM pulses are staggered. 
     
     
         9 . A system for refresh in a cache memory, comprising:
 at least one cache memory bank;   a bank controller local to, and in communication with, the at least one cache memory bank;   a centralized refresh controller in communication with the bank controller, the centralized refresh controller configured to perform a method, comprising:   generating a refresh time period (RTIM) pulse at the centralized refresh controller of the cache memory;   activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with the at least one cache memory bank;   receiving a refresh grant in response to activating the refresh request;   transmitting the refresh grant to the bank controller.   
     
     
         10 . The system of  claim 9 , wherein the RTIM pulse is generating at the beginning of a refresh time interval. 
     
     
         11 . The system of  claim 10 , wherein the refresh time period pulse denotes the beginning of an interval during which all EDRAM macros of the single cache memory bank must be refreshed to retain their contents. 
     
     
         12 . The system of  claim 9 , wherein the central refresh controller generates a new RTIM pulse every N clock cycles, where N is a number of clock cycles of a predetermined refresh period. 
     
     
         13 . The system of  claim 12 , wherein the predetermined refresh period is determined based upon at least one of system operating voltage and system temperature of the cache memory. 
     
     
         14 . The system of  claim 9 , wherein the refresh grant is received from a bank availability model in communication with the central refresh controller activating the refresh request, and the bank availability model is configured to perform a method, comprising:
 receiving the refresh request;   suppressing availability of the single cache memory bank in response to the received refresh request;   determining if there is an available time slot for granting the refresh request; and   issuing the refresh grant in response to the determining.   
     
     
         15 . The system of  claim 9 , wherein a plurality of different RTIM pulses are generated for a plurality of different bank controllers, each bank controller being local to, and associated with, only one cache memory bank of the cache memory, and each cache memory bank of the cache memory being associated with only one bank controller. 
     
     
         16 . The system of  claim 15 , wherein the plurality of different RTIM pulses are staggered. 
     
     
         17 . A computer implemented method of system refresh in a cache memory, the method comprising:
 generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory;   activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory;   receiving a refresh grant in response to activating the refresh request; and   transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.   
     
     
         18 . The method of  claim 17 , wherein the central refresh controller generates a new RTIM pulse every N clock cycles, where N is a number of clock cycles of a predetermined refresh period. 
     
     
         19 . The method of  claim 18 , wherein the predetermined refresh period is determined based upon at least one of system operating voltage and system temperature of the cache memory. 
     
     
         20 . The method of  claim 17 , wherein the refresh grant is received from a bank availability model in communication with the central refresh controller activating the refresh request, and the bank availability model is configured to perform a method, comprising:
 receiving the refresh request;   suppressing availability of the single cache memory bank in response to the received refresh request;   determining if there is an available time slot for granting the refresh request; and   issuing the refresh grant in response to the determining.   
     
     
         21 . The method of  claim 17 , wherein a plurality of different RTIM pulses are generated for a plurality of different bank controllers, each bank controller being local to, and associated with, only one cache memory bank of the cache memory, and each cache memory bank of the cache memory being associated with only one bank controller. 
     
     
         22 . The method of  claim 17 , wherein the plurality of different RTIM pulses are staggered.

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