Igbt transistor with protection against parasitic component activation and manufacturing process thereof

Abstract

An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region.

1 . An IGBT transistor comprising:
 a drift region;   at least one body region housed in said drift region and having a first type of conductivity; and   a conduction region, crossing said body region in a direction perpendicular to a surface of said drift region and having said first type of conductivity and a lower resistance than said body region;   characterized in that wherein said conduction region comprises a plurality of implant regions, arranged at respective depths from said surface of said drift region.   
     
     
         2 . The transistor according to  claim 1 , wherein said implant regions comprise a surface implant region and a plurality of buried implant regions contiguous to one another. 
     
     
         3 . The transistor according to  claim 2 , wherein one of said deep implant regions is contiguous to said drift region. 
     
     
         4 . The transistor according to  claim 2 , wherein said conduction region has a higher doping level than said body region. 
     
     
         5 . The transistor according to  claim 4 , wherein said deep implant regions have an intermediate doping level between said body region and said surface implant region. 
     
     
         6 . The transistor according to  claim 1 , wherein said drift region has a second type of conductivity, opposite to said first type of conductivity. 
     
     
         7 . The transistor according to  claim 6 , comprising at least one source region housed in said body region and having said second type of conductivity. 
     
     
         8 . The transistor according to  claim 7 , comprising gate regions arranged on said drift region and defining an opening above said conduction region. 
     
     
         9 . The transistor according to  claim 8 , wherein said conduction region is arranged centrally with respect to said opening. 
     
     
         10 . The transistor according to  claim 8  or  claim 9 , wherein said body region extends around said opening and is separated from said gate regions by gate-oxide regions and wherein portions of said body region immediately underlying said gate-oxide regions define channel regions. 
     
     
         11 . A process for manufacturing an IGBT transistor, comprising the steps of:
 providing, in a semiconductor wafer, a drift region;   forming, in said drift region, at least one body region having a first type of conductivity; and   forming a conduction region, crossing said body region in a direction perpendicular to a surface of said drift region and having said first type of conductivity and a resistance lower than that of said body region;   characterized in that wherein said step of forming said conduction region comprises:   carrying out a plurality of implantations of dopant species in said body region at respective depths from said surface of said drift region.   
     
     
         12 . The process according to  claim 11 , wherein said step of carrying out a plurality of implantations comprises carrying out a surface implantation for forming a surface implant region and a plurality of deep implantations for providing respective deep implant regions. 
     
     
         13 . The process according to  claim 12 , wherein said conduction region has a higher doping level than said body region. 
     
     
         14 . The process according to  claim 13 , wherein said deep implant regions have an intermediate doping level between said body region and that of said surface implant region. 
     
     
         15 . The process according to  claim 11 , wherein said drift region has a second type of conductivity, opposite to said first type of conductivity. 
     
     
         16 . The process according to  claim 11 , comprising the step of subjecting said semiconductor wafer to a thermal process for electrically activating the implanted dopant species, wherein said thermal process has a duration such as to prevent diffusion of the implanted dopant species. 
     
     
         17 . The process according to  claim 16 , wherein a duration of said thermal process is between 10 s and 30 s. 
     
     
         18 . The process according to  claim 16 , wherein said thermal process comprises to heating said wafer up to a temperature of between 1000° C. and 1150° C. 
     
     
         19 . The process according to  claim 16 , comprising the steps of:
 forming a gate-oxide layer on said drift region;   depositing a conductive polysilicon layer on said gate-oxide layer; and   shaping said conductive layer and said gate-oxide layer for forming gate regions, separated from said drift region by respective gate-oxide regions and defining openings above said drift region.   
     
     
         20 . The process according to  claim 19 , wherein said step of forming said body region comprises:
 introducing dopant species into said drift region through said openings; and   diffusing the dopant species introduced.